A 20Mbps sub-0.1nJ/b Transmitter for Capsule Endoscope Application
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초록
In this paper presents a high-speed and low-power transmitter for capsule endoscope application in CMOS 65nm process. The transmitter consists of a FSK modulator for high speed, low power modulation and a class-E Power Amplifier that can effectively transfer power to the antenna. The modulator has to secure sufficient loop bandwidth for high speed operation. Therefore, we implemented the fast FSK modulator using two frequency synthesizers (PLL). The frequency band used is the 420-440MHz band, which is a frequency that can minimize loss, and two frequency synthesizers are switched to 20Mbps. The power amplifier using series resonance at the output network, with frequency selective characteristics, a class-E switching power amplifier with 87% power efficiency at the output power of -16dBm. 1V was used for the supply voltage, and the DC power consumption was 1.7mW. The phase noise of the FSK modulator is -85dBc at 420MHz. The fabricated chip occupied a core area of 0.3mm*0.36mm, achieving sub-0.1nJ/b energy efficiency.
Abstract
In this paper presents a high-speed and low-power transmitter for capsule endoscope application in CMOS 65nm process. The transmitter consists of a FSK modulator for high speed, low power modulation and a class-E Power Amplifier that can effectively transfer power to the antenna. The modulator has to secure sufficient loop bandwidth for high speed operation. Therefore, we implemented the fast FSK modulator using two frequency synthesizers (PLL). The frequency band used is the 420-440MHz band, which is a frequency that can minimize loss, and two frequency synthesizers are switched to 20Mbps. The power amplifier using series resonance at the output network, with frequency selective characteristics, a class-E switching power amplifier with 87% power efficiency at the output power of -16dBm. 1V was used for the supply voltage, and the DC power consumption was 1.7mW. The phase noise of the FSK modulator is -85dBc at 420MHz. The fabricated chip occupied a core area of 0.3mm*0.36mm, achieving sub-0.1nJ/b energy efficiency.
참고문헌 (8)
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