Beamforming Transmitter IC for Far-Field Wireless Charging
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초록
This paper presents a wireless power transfer (WPT) system designed specifically for far-field charging scenarios, utilizing advanced beamforming technology. The system consists of a phase-shifting phase-locked loop (PLL) and a robust dual-band power amplifier (PA) capable of delivering high power with high efficiency. The PLL is engineered to synchronize with a reference clock frequency of 50 MHz and operates at frequencies of 5.8 GHz and 4.8 GHz, ideal for beamforming applications, particularly in the context of IoT devices. The PA architecture comprises two stages, integrating interstage and output baluns to optimize power matching. It directly amplifies the output from the 5.8 GHz PLL and boosts the 4.8 GHz PLL output by dividing it by two and then amplifying the resulting 2.4 GHz signal. This system is implemented using a 130-nm CMOS process, achieving VCO gains (KVCO) of 141.72 MHz/V and 83.5 MHz/V at 5.8 GHz and 4.8 GHz, respectively. Current consumption is measured at 281.4mA and 513.8mA at a 1.2V supply voltage for 5.8 GHz and 2.4 GHz, respectively. The PLL allows for a phase shift of 5.625° across the entire 360° range at frequencies of 5.8 GHz and 4.8 GHz, while the PA achieves output powers of 25.41dBm and 24.48dBm, respectively.
Abstract
This paper presents a wireless power transfer (WPT) system designed specifically for far-field charging scenarios, utilizing advanced beamforming technology. The system consists of a phase-shifting phase-locked loop (PLL) and a robust dual-band power amplifier (PA) capable of delivering high power with high efficiency. The PLL is engineered to synchronize with a reference clock frequency of 50 MHz and operates at frequencies of 5.8 GHz and 4.8 GHz, ideal for beamforming applications, particularly in the context of IoT devices. The PA architecture comprises two stages, integrating interstage and output baluns to optimize power matching. It directly amplifies the output from the 5.8 GHz PLL and boosts the 4.8 GHz PLL output by dividing it by two and then amplifying the resulting 2.4 GHz signal. This system is implemented using a 130-nm CMOS process, achieving VCO gains (KVCO) of 141.72 MHz/V and 83.5 MHz/V at 5.8 GHz and 4.8 GHz, respectively. Current consumption is measured at 281.4mA and 513.8mA at a 1.2V supply voltage for 5.8 GHz and 2.4 GHz, respectively. The PLL allows for a phase shift of 5.625° across the entire 360° range at frequencies of 5.8 GHz and 4.8 GHz, while the PA achieves output powers of 25.41dBm and 24.48dBm, respectively.
참고문헌 (7)
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