An 8G Hz SST Transmitter with Adjustable FIR and Pre-Emphasis Logic in 65nm CMOS
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In response to the escalating demands for high-speed communication and the necessity for effective channel loss compensation, this study introduces an advanced transmitter (TX) system with enhanced adaptability. This system integrates a sophisticated TX architecture, augmented by a pre-emphasis logic, and a three-tap Finite Impulse Response (FIR) filter, using TSMC's 65nm process technology. The core of the pre-emphasis architecture is a Voltage-Mode Driver topology, serving both as the primary driver and emphasis cell, supplemented by an additional logic to modulate the FIR's first tap. This modulation facilitates varied emphasis states, enabling tailored compensation for diverse channel losses. The FIR, realized through Current-Mode Logic (CML), optimizes power efficiency, while the driver configuration, composed of Source Series Termination (SST) drivers, ensures a robust output swing. Incorporating SST drivers’ ushers in a hybrid impedance control approach, merging conventional analog-loop control with impedance regulation via the SST driver slices. Simulation results show that the system achieves speeds of up to 8GHz and an output swing of 1.2V while maintaining an eye width of 0.8 Unit Intervals (UI).
Abstract
In response to the escalating demands for high-speed communication and the necessity for effective channel loss compensation, this study introduces an advanced transmitter (TX) system with enhanced adaptability. This system integrates a sophisticated TX architecture, augmented by a pre-emphasis logic, and a three-tap Finite Impulse Response (FIR) filter, using TSMC's 65nm process technology. The core of the pre-emphasis architecture is a Voltage-Mode Driver topology, serving both as the primary driver and emphasis cell, supplemented by an additional logic to modulate the FIR's first tap. This modulation facilitates varied emphasis states, enabling tailored compensation for diverse channel losses. The FIR, realized through Current-Mode Logic (CML), optimizes power efficiency, while the driver configuration, composed of Source Series Termination (SST) drivers, ensures a robust output swing. Incorporating SST drivers’ ushers in a hybrid impedance control approach, merging conventional analog-loop control with impedance regulation via the SST driver slices. Simulation results show that the system achieves speeds of up to 8GHz and an output swing of 1.2V while maintaining an eye width of 0.8 Unit Intervals (UI).
참고문헌 (16)
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