Capacitor-Free Event-Based Asynchronous Digital LDO Regulator with 99.99% Current Efficiency
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This paper proposes a high-performance digital low-dropout regulator (DLDO) for wearable devices and IoT applications. The proposed DLDO circuit design provides fast stability and low power consumption using a PID controller and event-driven digital feedback control. The circuit utilizes a high-speed Flash-SAR ADC to feedback on the output, enabling real-time adjustment of the PID controller parameters to quickly adapt to external environmental changes and achieve a fast settling time. The proposed event-driven method minimizes circuit operation to reduce power consumption. Additionally, the limit-cycle oscillation typically occurring in the steady state is suppressed, thereby reducing output voltage ripple. The circuit is fabricated using a 55-nm CMOS process, with a chip area of 1800 x 1820 um². The proposed design supports an input voltage range of 0.5 – 1.2 V and an output voltage range of 0.4 – 1 V. It achieves a fast-settling time of 252 ns and a low current consumption of 1.7 μA at a 50MHz operating frequency. The peak current efficiency is 99.99%, with a maximum load current of 70 mA. The load regulation is 0.13 mV/mA, and the line regulation is 0.01 V/V.
Abstract
This paper proposes a high-performance digital low-dropout regulator (DLDO) for wearable devices and IoT applications. The proposed DLDO circuit design provides fast stability and low power consumption using a PID controller and event-driven digital feedback control. The circuit utilizes a high-speed Flash-SAR ADC to feedback on the output, enabling real-time adjustment of the PID controller parameters to quickly adapt to external environmental changes and achieve a fast settling time. The proposed event-driven method minimizes circuit operation to reduce power consumption. Additionally, the limit-cycle oscillation typically occurring in the steady state is suppressed, thereby reducing output voltage ripple. The circuit is fabricated using a 55-nm CMOS process, with a chip area of 1800 x 1820 um². The proposed design supports an input voltage range of 0.5 – 1.2 V and an output voltage range of 0.4 – 1 V. It achieves a fast-settling time of 252 ns and a low current consumption of 1.7 μA at a 50MHz operating frequency. The peak current efficiency is 99.99%, with a maximum load current of 70 mA. The load regulation is 0.13 mV/mA, and the line regulation is 0.01 V/V.