Dynamic Performance Enhancement of a Current-Steering DAC Using Tree-Structured Routing and Power Mesh-Based SI/PI Optimization
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As broadband communication systems demand increasingly higher data rates, the role of High-speed DACs has become essential. Time-Interleaved DAC (TI-DAC) architectures are widely employed to achieve higher sampling speeds by operating multiple sub-DAC channels in parallel. However, employing two sub-channels in a Time-Interleaved structure increases array area and exacerbates power integrity challenges, which can further degrade dynamic performance typically measured by SFDR. Moreover, the physical layout of each sub-DAC includes over 126-unit cells, and non-uniform routing paths between these cells can lead to dynamic mismatch in current summation, resulting in SFDR degradation. Layout-level optimization and PDN enhancement are applied, improving the SFDR from 41.5dB to 52.5dB.
Abstract
As broadband communication systems demand increasingly higher data rates, the role of High-speed DACs has become essential. Time-Interleaved DAC (TI-DAC) architectures are widely employed to achieve higher sampling speeds by operating multiple sub-DAC channels in parallel. However, employing two sub-channels in a Time-Interleaved structure increases array area and exacerbates power integrity challenges, which can further degrade dynamic performance typically measured by SFDR. Moreover, the physical layout of each sub-DAC includes over 126-unit cells, and non-uniform routing paths between these cells can lead to dynamic mismatch in current summation, resulting in SFDR degradation. Layout-level optimization and PDN enhancement are applied, improving the SFDR from 41.5dB to 52.5dB.