비트라인 트래킹을 위한 replica 기술에 관한 연구
Replica Technique regarding research for Bit-Line tracking
1
조회
0
다운로드
0
인용
0
참고문헌
키워드
초록
Replica bit-line technique is used for making enable signal of sense amplifier which accurately tracks bit-line of SRAM. However, threshold voltage variation in the replica bit-line circuit changes the cell current, which results in variation of the sense amplifier enable time, TSAE. The variation of TSAE makes the sensing operation unstable. In this paper, in addition to conventional replica bit-line delay (RBLconv), dual replica bit-line delay (DRBD) and multi-stage dual replica bit-line delay (MDRBD) which are used for reducing TSAE variation are briefly introduced, and the maximum possible number of on-cell which can satisfy 6σ sensing yield is determined through simulation at a supply voltage of 0.6V with 14nm FinFET technology. As a result, it is observed that performance of DRBD and MDRBD is improved 24.4% and 48.3% than RBLconv and energy consumption is reduced which 8% and 32.4% than RBLconv.
Abstract
Replica bit-line technique is used for making enable signal of sense amplifier which accurately tracks bit-line of SRAM. However, threshold voltage variation in the replica bit-line circuit changes the cell current, which results in variation of the sense amplifier enable time, TSAE. The variation of TSAE makes the sensing operation unstable. In this paper, in addition to conventional replica bit-line delay (RBLconv), dual replica bit-line delay (DRBD) and multi-stage dual replica bit-line delay (MDRBD) which are used for reducing TSAE variation are briefly introduced, and the maximum possible number of on-cell which can satisfy 6σ sensing yield is determined through simulation at a supply voltage of 0.6V with 14nm FinFET technology. As a result, it is observed that performance of DRBD and MDRBD is improved 24.4% and 48.3% than RBLconv and energy consumption is reduced which 8% and 32.4% than RBLconv.
참고문헌 (4)
- M. Khellah, "Read and write circuit assist techniques for improving Vccmin of dense 6T SRAM cell", Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT 2008. IEEE International Conference on, pp.185~188 (2008)
- Y. Niki, "A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generat ion of SRAM Sense Amplifiers", Solid-State Circuits, IEEE Journal of, 46, pp.2545~2551 (2011)
- W. Jianhui, "A Multiple-Stage Parallel Replica-Bitli ne Delay Addition Technique for Reducing Timing Variation of SRAM Sense Amplifiers", Circuits and Systems I I : Express Briefs, IEEE Transactions on, 61, pp.264~268 (2014)
- C.-y. Peng, "Multi-stage dual replica bit-line delay technique for process-variationrobust timing of low voltage SRAM sense amplifier", Frontiers of Information Technology & Electronic Engineering, 16, pp.700~706 (2015)