Analysis of Offset-Canceled DRAM Sense Amplifier
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This paper analyzes a DRAM sense amplifier (SA) architecture employing an offset cancellation technique using parasitic bit-line capacitance. The offset is stored through a diode-connected configuration without requiring additional calibration circuits, enabling a compact design. A prototype was fabricated in a TSMC 65 nm CMOS process and operated at 400 MHz. A built-in self-test (BIST) evaluates sensing accuracy by performing repeated write-and-read operations across 64 SAs. Measurements show that the standard deviation of input-referred offset decreases with longer offset cancellation (OC) time and saturates near 5 ns, indicating an optimal tradeoff between performance and power. The main sensing (MS) duration has minimal effect on offset characteristics, confirming that a 5 ns MS period ensures reliable operation. The architecture achieves effective offset cancellation with minimal overhead, making it well suited for scaled DRAM applications.
Abstract
This paper analyzes a DRAM sense amplifier (SA) architecture employing an offset cancellation technique using parasitic bit-line capacitance. The offset is stored through a diode-connected configuration without requiring additional calibration circuits, enabling a compact design. A prototype was fabricated in a TSMC 65 nm CMOS process and operated at 400 MHz. A built-in self-test (BIST) evaluates sensing accuracy by performing repeated write-and-read operations across 64 SAs. Measurements show that the standard deviation of input-referred offset decreases with longer offset cancellation (OC) time and saturates near 5 ns, indicating an optimal tradeoff between performance and power. The main sensing (MS) duration has minimal effect on offset characteristics, confirming that a 5 ns MS period ensures reliable operation. The architecture achieves effective offset cancellation with minimal overhead, making it well suited for scaled DRAM applications.