고해상도 저전력 센서 시스템을 위한 아날로그-디지털 변환기의 구조 개선
Architecture Improvement of Analog-Digital Converter for High-Resolution Low-Power Sensor Systems
0
조회
0
다운로드
0
인용
0
참고문헌
키워드
초록
센서 시스템의 아날로그-디지털 변환기(ADC: analog-to-digital converter)에서는 높은 해상도, 낮은 전력 소모, 높은 신호 대역폭이 요구된다. 시그마-델타 ADC는 높은 차수 구조와 높은 오버샘플링 비를 통해 고해상도를 얻을 수 있으나 전력 소모가 높고 신호 대역폭이 낮다. 연속 근사 레지스터(SAR: successive-approximation-register) ADC의 경우 저전력 동작이 가능하나 공정상 부정합으로 인해 해상도에 한계가 있다. 본 논문에서는 이러한 단점들을 극복하기 위한 ADC 구조 개선에 대해 살펴본다.
Abstract
In sensor systems, ADC (analog-to-digital converter) demands high resolution, low power consumption, and high signal bandwidth. Sigma-delta ADC achieves high resolution by high order structure and high over-sampling ratio, but it suffers from high power consumption and low signal bandwidth. SAR (successive- approximation-register) ADC achieves low power consumption, but there is a limitation to achieve high resolution due to process mismatch. This paper surveys architecture improvement of ADC to overcome these problems.
참고문헌 (20)
- W. Kester, "Which ADC Architecture Is Right for Your Application?", Analog Dialogue (2005)
- 최정열, "고해상도, 저잡음 캐패시턴스 디지털 신호 변환기", 전자공학회논문지, 54(12), pp.81~87 (2017), 대한전자공학회
- "Understanding SAR ADCs: Their Architecture and Comparison with Other ADCs"[URL]
- S. Choi, "An 84.6-dB-SNDR and 98.2-dB-SFDR Residue-Integrated SAR ADC for Low-Power Sensor Applications", IEEE Journal of Solid-State Circuits, 53(2), pp.404~417 (2018)[DOI]
- S. Wu, "A 81-dB Dynamic Range 16-MHz Bandwidth Delta-Sigma Modulator Using Background Calibration", IEEE Journal of Solid-State Circuits, 48(9), pp.2170~2179 (2013)[DOI]
- F. Mostert, "5.1 A <TEX>$5{\times}80W$<", TEX> 0.004% THD+N Automotive Multiphase Class-D Audio Amplifier with Integrated Low-latency <TEX>${\Delta}{\Sigma}$<, Proc. of IEEE International Solid-State Circuits Conference, pp.2017[DOI]
- C. Chen, "History, present state-of-art and future of incremental ADCs", Proc. of European Solid-State Circuits Conference, pp.83~86 (2016)
- 정영재, "단일-극 커패시터 방식의 터치센서를 위한 Incremental 델타-시그마 아날로그-디지털 변환기 설계", 전기전자학회논문지, 17(3), pp.234~240 (2013), 한국전기전자학회[DOI]
- Y. Chae, "A <TEX>$6.3{\mu}W$<", TEX> 20 bit Incremental Zoom-ADC with 6 ppm INL and <TEX>$1{\mu}V$<, IEEE Journal of Solid-State Circuits, pp.2013, 48(12)[DOI]
- B. Gonen, "A Dynamic Zoom ADC with 109-dB DR for Audio Applications", IEEE Journal of Solid-State Circuits, 52(6), pp.1542~1550 (2017)[DOI]
- S. Karmakar, "A <TEX>$280{\mu}W$<", TEX> dynamic-zoom ADC with 120dB DR and 118dB SNDR in 1kHz BW, 2018, 238~240
- "Continuous-Time Sigma-Delta ADCs"[URL]
- A. Hart, "A 1 GHz Bandwidth Low-Pass Delta-Sigma ADC With 20-50 GHz Adjustable Sampling Rate", IEEE Journal of Solid-State Circuits, 44(5), pp.1401~1414 (2009)[DOI]
- C. Weng, "A Continuous-Time Delta-Sigma Modulator Using ELD-Compensation-Embedded SAB and DWA-Inherent Time-Domain Quantizer", IEEE Journal of Solid-State Circuits, 51(5), pp.1235~1245 (2016)[DOI]
- A. Sukumaran, "Design of Continuous-Time Delta-Sigma Modulators With Dual Switched-Capacitor Return-to-Zero DACs", IEEE Journal of Solid-State Circuits, 51(7), pp.1619~1629 (2016)[DOI]
- B. Ginsburg, "500-MS", s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC, 2007, pp.42(4), 739~747
- M. Kim, "A 12-bit 200-kS", s SAR ADC with hybrid RC DAC, 2014, 185~188
- A. AlMarashli, "A Nyquist Rate SAR ADC Employing Incremental Sigma Delta DAC Achieving Peak SFDR = 107 dB at 80 kS", s, 2018, pp.53(5), 1493~1507
- J. McNeill, "All-digital background calibration of a successive approximation ADC using the 'Split ADC' architecture", IEEE Trans. Circuits Syst. I, 58(10), pp.2355~2365 (2011)[DOI]
- J. Shen, "A 16-bit 16-MS", s SAR ADC With On-Chip Calibration in 55-nm CMOS, 2018, pp.53(4), 1149~1160