응답 시간을 향상 시킨 외부 커패시터가없는 Low-Dropout 레귤레이터 회로
A Capacitorless Low-Dropout Regulator With Enhanced Response Time
1
조회
0
다운로드
2
인용
0
참고문헌
키워드
초록
본 논문에서는 외부 커패시터가 없는 low-dropout (LDO) 레귤레이터를 설계하였으며, 대기 전류는 4.5㎂ 이다. 제안하는 LDO 레귤레이터는 정밀한 로드 레귤레이션과 빠른 응답 속도를 만족하기 위해 두 개의 증폭기를 사용 하였고, 높은 이득을 갖는 증폭기와 빠른 속도 및 높은 슬루율을 가지는 증폭기로 구성 되어 있다. 이와 함께 패스 트랜지스터의 게이트에 존재하는 큰 기생 커패시터에 전류를 빠르게 충·방전시키기 위해, 전류 부스팅 회로를 추가하였다. 이를 통해 부하 전류 변화 시 응답 시간을 향상 시키게 된다. 설계된 회로는 0.11-㎛ CMOS 공정으로 제작되었다. 최대 200㎃ 의 부하 전류를 구동할 수 있으며, 출력 전압 변동은 260㎷, 회복 시간은 0.8㎲ 을 측정하였다.
Abstract
In this paper, an output-capacitorless, low-dropout (LDO) regulator is designed, which consumes 4.5㎂ quiescent current. Proposed LDO regulator is realized using two amplifier for good load regulation and fast response time, which provide high gain, high bandwidth, and high slew rate. In addition, a one-shot current boosting circuit is added for current control to charge and discharge the parasitic capacitance at the pass transistor gate. As a result, response time is improved during load-current transition. The designed circuit is implemented through a 0.11-㎛ CMOS process. We experimentally verify output voltage fluctuation of 260㎷ and recovery time of 0.8㎲ at maximum load current 200㎃.
참고문헌 (16)
- C. -J. Park, "External capacitor-less low drop-out regulator with 25 dB superior power supply rejection in the 0. 4-4 MHz range", IEEE J. Solid-State Circuits, 49(2), pp.486~501 (2014)
- C. K. Chava, "A frequency compensation scheme for LDO voltage regulators", IEEE Trans. Circuits Syst. I, Reg. Papers, 51(6), pp.1041~1050 (2004)
- H. -C. Lin, "An active-frequency compensation scheme for CMOS low-dropout regulators with transient-response improvement", IEEE Trans. Circuits Syst. II, Exp. Briefs, 55(9), pp.853~857 (2008)
- K. Keikhosravy, "A 0. 13-㎛ CMOS low-power capacitor-less LDO regulator using bulk-modulation technique", IEEE Trans. Circuits Syst. I, Reg. Papers, 61(11), pp.3105~3114 (2014)
- M. Ho, "A low-power fast-transient 90-nm low-dropout regulator with multiple small-gain stages", IEEE J. Solid-State Circuits, 45, pp.2466~2476 (2010)
- C. Zhan, "Output-capacitor-free adaptively biased low-dropout regulator for system-on-chips", IEEE Trans. Circuits Syst. I, Reg. Papers, 57(5), pp.1017~1028 (2010)
- G. A. Rincon-Mora, "A low-voltage, low quiescent current, low drop-out regulator", IEEE J. Solid-State Circuits, 33(1), pp.36~44 (1998)
- R. J. Milliken, "Full on-chip CMOS low-dropout voltage regulator", IEEE Trans. Circuits Syst. I, Reg. Papers, 54(9), pp.1879~1890 (2007)
- W. -C. Chen, "A switchable digital-analog low-dropout regulator for analog dynamic voltage scaling technique", IEEE J. Solid-State Circuits, 49(3), pp.740~750 (2014)
- X. Ming, "An ultrafast adaptively biased capacitorless LDO with dynamic charging control", IEEE Trans. Circuits Syst. II, Exp. Brief, 59(1), pp.40~44 (2012)
- S. S. Chong, "A 0. 9-㎂ quiescent current output-capacitorless LDO regulator with adaptive power transistors in 65-nm CMOS", IEEE Trans. Circuits Syst. I, Reg. Papers, 60(4), pp.1072~1081 (2013)
- K. N. Leung, "A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation", IEEE J. Solid-State Circuits, 38(10), pp.1691~1702 (2003)
- J. Roh, "High-gain class-AB OTA with low quiescent current", Analog Integr. Circuits Signal Process, 47(2), pp.225~228 (2006)
- P. Y. Or, "An output-capacitorless low-dropout regulator with direct voltage-spike detection", IEEE J. Solid-State Circuits, 45(2), pp.458~466 (2010)
- X. Qu, "An ultralow-power fast-transient capacitor-free low-dropout regulator with assistant push-pull output stage", IEEE Trans. Circuits Syst. II, Exp. Briefs, 60(2), pp.96~100 (2013)
- Y. Kim, "A capacitorless LDO regulator with fast feedback technique and low-quiescent current error amplifier", IEEE Trans. Circuits Syst. II, Exp. Briefs, 60(6), pp.326~330 (2013)