안티-바운드리 스위칭 디지털 지연고정루프
An Anti-Boundary Switching Digital Delay-Locked Loop
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참고문헌
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초록
본 논문에서는 고속 DDR3/DDR4 SDRAM을 위한 새로운 디지털 지연고정루프 (delay-locked loop: DLL)를 제안한다. 제안하는 디지털 DLL은 디지털 지연라인의 boundary switching 문제에 의한 jitter 증가 문제를 제거하기 위하여 위상보간 (phase interpolation) 방식의 파인지연라인 (fine delay line)을 채택하였다. 또한, 제안하는 디지털 DLL은 harmonic lock 문제를 제거하기 위하여 새로운 점진직 검색 (gradual search) 알고리즘을 사용한다. 제안하는 디지털 DLL은 1.1V, 38-nm CMOS DRAM 공정으로 설계되었으며, 0.25-2.0 GHz의 주파수 동작 영역을 가진다. 2.0 GHz에서 1.1 ps의 피크-투-피크 (p-p) 지터를 가지며, 약 13 mW의 전력소모를 가진다.
Abstract
In this paper, we propose a new digital delay-locked loop (DLL) for high-speed DDR3/DDR4 SDRAMs. The proposed digital DLL adopts a fine delay line using phase interpolation to eliminate the jitter increase problem due to the boundary switching problem. In addition, the proposed digital DLL utilizes a new gradual search algorithm to eliminate the harmonic lock problem. The proposed digital DLL is designed with a 1.1 V, 38-nm CMOS DRAM process and has a frequency operating range of 0.25-2.0 GHz. It has a peak-to-peak jitter of 1.1 ps at 2.0 GHz and has a power consumption of about 13 mW
참고문헌 (7)
- Ji-Hoon Lim, "A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%–80% Input Duty Cycle for SDRAMs", IEEE Transactions on Circuits and Systems II: Express Briefs, 63(2), pp.141~145 (2016), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
- S. Han, "A high-resolution wide-range dual-loop digital delay-locked loop using a hybrid search algorithm", IEEE Asian Solid State Circuits Conference (A-SSCC), pp.293~296 (2012)
- Junsub Yoon, "A fast-locking harmonic-free digital DLL for DDR3 and DDR4 SDRAMs", IEICE Electronics Express, 14(2), pp.20161020~20161020 (2017), Institute of Electronics, Information and Communications Engineers (IEICE)[DOI]
- Lei Wang, "An Implementation of Fast-Locking and Wide-Range 11-bit Reversible SAR DLL", IEEE Transactions on Circuits and Systems II: Express Briefs, 57(6), pp.421~425 (2010), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
- Rong-Jyi Yang, "A 40–550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm", IEEE Journal of Solid-State Circuits, 42(2), pp.361~373 (2007), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
- Ji-Hoon Lim, "A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%–80% Input Duty Cycle for SDRAMs", IEEE Transactions on Circuits and Systems II: Express Briefs, 63(2), pp.141~145 (2016), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
- Lei Wang, "An Implementation of Fast-Locking and Wide-Range 11-bit Reversible SAR DLL", IEEE Transactions on Circuits and Systems II: Express Briefs, 57(6), pp.421~425 (2010), Institute of Electrical and Electronics Engineers (IEEE)[DOI]