고속-락킹 디지털 주파수 증배기
A Fast-Locking All-Digital Frequency Multiplier
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참고문헌
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초록
안티-하모닉락 기능을 가지는 고속-락킹 MDLL 기반의 디지털 클락 주파수 증배기를 소개한다. 제안하는 디지털 주파수증배기는 하모닉락 문제 없이 빠른 락킹 시간을 구현하기 위하여 새로운 MSB-구간 검색 알고리즘을 사용한다. 제안하는 디지털 MDLL 주파수 증배기는 65nm CMOS 공정으로 설계되었으며, 1 GHz ～ 3 GHz의 출력 동작주파수 영역을 가진다. 제안하는 디지털 MDLL은 프로그래머블한 N/M (N=1, 4, 5, 8, 10, M=1, 2, 3)의 분수배 주파수 증배 기능을 제공한다. 제안하는MDLL은 1GHz에서 3.52 mW의 전력을 소모하고, 14.07 ps의 피크-투-피크 (p-p) 지터를 갖는다.
Abstract
A fast-lock multiplying delay-locked loop (MDLL)-based digital clock frequency multiplier with an anti-harmonic lockcapability is presented. The proposed digital frequency multiplier utilizes a new most-significant bit (MSB)-intervalsearch algorithm to achieve fast-locking time without harmonic lock problems. The proposed digital MDLL frequencymultiplier is designed in a 65nm CMOS process, and the operating output frequency range is from 1 GHz to 3 GHz. Thedigital MDLL provides a programmable fractional-ratio frequency multiplication ratios of N/M, where N = 1, 4, 5, 8, 10and M = 1, 2, 3, respectively. The proposed MDLL consumes 3.52 mW at 1GHz and achieves a peak-to-peak (p-p)output clock jitter of 14.07 ps.
참고문헌 (8)
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