공정 편차가 하이브리드 MOSFET-CNTFET 기반SRAM의 성능에 미치는 영향에 대한 연구
A Study on the Effect of Process Variation on the Performance of Hybrid MOSFET-CNTFET based SRAM
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초록
전통적인 실리콘 기반 반도체 소자 보다 높은 성능과 다양한 활용성으로 차세대 반도체 후보로 높은 관심 받고 있는 CNTFET은CNT 배치와 같은 CNTFET만의 고유한 공정 편차가 아직 성숙되지 않아 상용화에 어려움을 겪고 있다. 이러한 어려움을 극복하고자 반복적인 회로 구성으로 공정 편차의 영향을 적게 받는 회로를 MOSFET-CNTFET 기반 하이브리드 회로로 구현하여 CNTFET의 장점을 취하고 단점을 보완하고자 하는 수많은 연구들이 지속적으로 수행되어 왔다. 본 논문에서는 하이브리드 SRAM의 성능이기존의 MOSFET SRAM 또는 CNTFET SRAM에 존재하는 반도체 공정 변화에 의해 얼마나 변화될 수 있는지를 비교하였다. 시뮬레이션 결과, CNT 밀도를 32nm 당 7개에서 9개 사이로 유지할 수 있다면, hybrid SRAM은 기존 MOSFET SRAM보다 읽기 동작에서 그리고 쓰기 동작에서 공정 편차에 대한 강건성이 각각 약 2.6배 그리고 약 1.1배 있음을 보여준다
Abstract
CNTFET, which is receiving high attention as a next-generation semiconductor candidate due to its higherperformance and various utilization than traditional silicon-based semiconductor devices, is having difficulty incommercialization because its unique process deviation such as CNT placement has not yet matured. To overcomethis difficulty, numerous studies have been continuously conducted to take advantages of CNTFET and compensateits weakness by implementing circuits, which are less affected by process deviation due to repetitive circuitplacement, into MOSFET-CNTFET based hybrid circuits. This paper compares how much the performance of thehybrid SRAM can be changed by semiconductor process variation existing in the traditional MOSFET SRAM orCNTFET SRAM. Simulation results show that, if the CNT density can be maintained between 7 and 9 per 32nm,hybrid SRAM is about 2.6 times and about 1.1 times more robust to process deviation than conventional MOSFETSRAM in read and write operations, respectively.
참고문헌 (21)
- Gage Hills, "Modern microprocessor built from complementary carbon nanotube transistors", Nature, 572(7771), pp.595~602 (2019), Springer Science and Business Media LLC[DOI]
- Yulim An, "Wafer-scale striped network transistors based on purified semiconducting carbon nanotubes for commercialization", Nanotechnology, 34(40), pp.405202~ (2023), IOP Publishing[DOI]
- Li Xiang, "Conformable Carbon Nanotube Thin Film Transistors on Ultrathin Flexible Substrates", IEEE Transactions on Electron Devices, 70(6), pp.3106~3111 (2023), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
- Sagar Shrestha, "Improving Stability of Roll-to-Roll (R2R) Gravure-Printed Carbon Nanotube-Based Thin Film Transistors via R2R Plasma-Enhanced Chemical Vapor-Deposited Silicon Nitride", Nanomaterials, 13(3), pp.559~ (2023), MDPI AG[DOI]
- Zhongyu Li, "Toward the Commercialization of Carbon Nanotube Field Effect Transistor Biosensors", Biosensors, 13(3), pp.326~ (2023), MDPI AG[DOI]
- Chenwei Fan, "Monolithic Three-Dimensional Integration of Carbon Nanotube Circuits and Sensors for Smart Sensing Chips", ACS Nano, 17(11), pp.10987~10995 (2023), American Chemical Society (ACS)[DOI]
- E. Abbasian, "A High-Performance and Energy-Efficient Ternary Multiplier Using CNTFETs", Arabian Journal for Science and Engineering (2023)
- Shobhit Kareer, "Metallic CNT Tolerant Field Effect Transistor Using Dielectrophoresis", IEEE Open Journal of Nanotechnology, 4, pp.95~101 (2023), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
- Ivan Sanchez Esqueda, "Aligned Carbon Nanotube Synaptic Transistors for Large-Scale Neuromorphic Computing", ACS Nano, 12(7), pp.7352~7361 (2018), American Chemical Society (ACS)[DOI]
- S. Jogad, "CNTFET based comparators:design, simulation and comparative analysis", Analog Integrated Circuits and Signal Processing, 114, pp.265~273 (2023)[DOI]
- Elham Esmaeili, "A high‐efficient imprecise discrete cosine transform block based on a novel full adder and Wallace multiplier for bioimages compression", International Journal of Circuit Theory and Applications, 51(6), pp.2942~2965 (2023), Wiley[DOI]
- E. Tavakkolia, "Comparison and design of energy-efficient approximate multiplier schemes for image processing by CNTFET", International Journal of Electronics, pp.1~22 (2023)[DOI]
- N. Patil, "Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(10), pp.1725~1736 (2008), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
- Katherine R. Jinkins, "Aligned 2D carbon nanotube liquid crystals for wafer-scale electronics", Science Advances, 7(37) (2021), American Association for the Advancement of Science (AAAS)[DOI]
- Ashish Sachdeva, "A carbon nano-tube field effect transistor based stable, low-power 8T static random access memory cell with improved write access time", AEU - International Journal of Electronics and Communications, 162, pp.154565~ (2023), Elsevier BV[DOI]
- Ashish Sachdeva, "A CNTFET Based Bit-Line Powered Stable SRAM Design for Low Power Applications", ECS Journal of Solid State Science and Technology, 12(4), pp.041006~ (2023), The Electrochemical Society[DOI]
- Lokesh Soni, "A Novel CNTFET Based Schmitt-Trigger Read Decoupled 12T SRAM Cell with High Speed, Low Power, and High Ion", Ioff Ratio, 2023, pp.167, 154669~[DOI]
- 조근호, "하이브리드 MOSFET-CNTFET 기반 SRAM 디자인 방법에 관한 연구", 전기전자학회논문지, 27(1), pp.65~70 (2023), 한국전기전자학회
- "PTM Models"[URL]
- "CNFET Models"[URL]
- Geunho Cho, "Circuit-Level Simulation of a CNTFET With Unevenly Positioned CNTs by Linear Programming", IEEE Transactions on Device and Materials Reliability, 14(1), pp.234~244 (2014), Institute of Electrical and Electronics Engineers (IEEE)[DOI]