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CTF-F 구조를 가진 3D NAND Flash Memory에서Gate Controllability 분석

The Analysis of Gate Controllability in 3D NAND Flash Memory with CTF-F Structure

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초록

본 논문은 Charge Trap Flash using Ferroelectric(CTF-F) 구조를 가진 3D NAND Flash Memory gate controllability에대해 분석했다. Ferroelectric 물질인 HfO2는 polarization 이외에도 high-k 라는 특징을 가진다. 이러한 특징으로 인해CTF-F 구조에서 gate controllability가 증가하고 Bit Line(BL)에서 on/off 전류특성이 향상된다. Simulation 결과 CTF-F 구조에서 String Select Line(SSL)과 Ground Select Line(GSL)의 채널길이는 100 nm로 기존 CTF 구조에 비해 33% 감소했지만 거의 동일한 off current 특성을 확인했다. 또한 program operation에서 channel에 inversion layer가 더 강하게 형성되어BL을 통한 전류가 약 2배 증가한 것을 확인했다.

Abstract

In this paper, we analyzed the gate controllability of 3D NAND Flash Memory with Charge Trap Flash usingFerroelectric (CTF-F) structure. HfO2, a ferroelectric material, has a high-k characteristic besides polarization. Due tothese characteristics, gate controllability is increased in CTF-F structure and on/off current characteristics are improvedin Bit Line(BL). As a result of the simulation, in the CTF-F structure, the channel length of String Select Line(SSL) andGround Select Line(GSL) was 100 nm, which was reduced by 33% compared to the conventional CTF structure, butalmost the same off-current characteristics were confirmed. In addition, it was confirmed that the inversion layer wasformed stronger in the channel during the program operation, and the current through the BL was increased by about 2times.

참고문헌 (13)

  1. Y. Jeong, "Study of Program Scheme using Ferroelectric Material in 3D NAND Flash Memory", ICEIC, 360(362), pp.19~22 (2020)[DOI]
  2. I. Ham, "Ferroelectric Polarization Aided Low Voltage Operation of 3D NAND Flash Memories", Electronics, 10(1), pp.38~ (2021)[DOI]
  3. Y. Seo, "Charge trap flash memory using ferroelectric materials as a blocking layer", Appl. Phys. Lett, 100, pp.173507~ (2012)[DOI]
  4. M. Kang, "The compact modeling of channel potential in sub-30nm NAND flash cell string", IEEE Electron Device Lett, 33, pp.321~323 (2012)[DOI]
  5. Y. Park, "Scaling and reliability of NAND flash devices", Proceedings of the 2014 IEEE International Reliability Physics Symposium,, pp.1~5 (2014)
  6. M. Kang, "An accurate compact model considering direct-channel in-terference of adjacent cells in sub-30-nm NAND flash technologies", IEEE Electron Device Lett, 33, pp.1114~1116 (2012)[DOI]
  7. Y. Kim, "Predictive modeling of channel potential in 3-D NAND flash memory", IEEE Trans. Electron Devices, 61, pp.3901~3904 (2014)[DOI]
  8. Y. Li, "3D NAND Memory and Its Application in Solid-State Drives : Architecture, Reliability, Flash Management Techniques, and Current Trends", in IEEE Solid-State Circuits Magazine, 12(4), pp.56~65 (2020)[DOI]
  9. Y. Jeong, "Optimal dummy word line condition to suppress hot carrier injection phenomenon due to the natural local self-boosting effect in 3D NAND flash memory", Jpn. J. Appl. Phys, 59, pp.1~5 (2020)[DOI]
  10. J. -M. Sim, "A New Read Scheme for Alleviating Cell-to-Cell Interference in Scaled-Down 3D NAND Flash Memory", Electronics, 9, pp.2020~[DOI]
  11. S. Choi, "A Novel Structure and Operation Scheme of Vertical Channel NAND Flash with Ferroelectric Memory for Multi String Operations", Electronics, 10(1), pp.32~ (2021)[DOI]
  12. J-M. Sim, "Gate All around with Back Gate NAND Flash Structure for Excellent Reliability Characteristics in Program Operation", Electronics, 10(15), pp.1828~ (2021)
  13. S. Choi, "Floating Filler (FF) in an Indium Gallium Zinc Oxide (IGZO) Channel Improves the Erase Performance of Vertical Channel NAND Flash with a Cell-on-Peri (COP) Structure", Electronics, 10(13), pp.1561~ (2021)[DOI]

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