본문 바로가기
KERD
논문KCI 등재

3D NAND Flash Memory에 Ferroelectric Material을사용한 Current Path 개선

Improvement of Current Path by Using Ferroelectric Material in 3D NAND Flash Memory

1

조회

0

다운로드

1

인용

0

참고문헌

키워드

초록

본 논문에서는 3D NAND Flash memory의 O/N/O(Oxide/Nitride/Oxide) 구조와 blocking oxide를 ferroelectric material로 대체한 O/N/F(Oxide/Nitride/Ferroelectric) 구조의 current path를 분석했다. O/N/O 구조는 Vread가 인가되면 neighboringcell의 E-field로 인해 current path가 channel 후면에 형성된다. 반면 O/N/F 구조는 ferroelectric material의 polarization으로 인해 electron이 channel 전면으로 이동하여 current path가 전면에 형성된다. 또한 channel thickness와 channel length에 따른 소자 특성을 분석했다. 분석 결과 O/N/F 구조의 전면 electron current density 증가는 O/N/O 구조보다 2.8배 더 높았고 O/N/F 구조의 전면 electron current density 비율이 17.7% 높았다. 따라서 O/N/O 구조보다 O/N/F 구조에서 전면current path가 더 효과적으로 형성된다.

Abstract

In this paper, we analyzed the current path in the O/N/O (Oxide/Nitride/Oxide) structure of 3D NAND Flashmemory and in the O/N/F (Oxide/Nitride/Ferroelectric) structure where the blocking oxide is replaced by aferroelectric. In the O/N/O structure, when Vread is applied, a current path is formed on the backside of thechannel due to the E-fields of neighboring cells. In contrast, the O/N/F structure exhibits a current path formedon the front side due to the polarization of the ferroelectric material, causing electrons to move toward thechannel front. Additionally, we performed an examination of device characteristics considering channel thicknessand channel length. The analysis results showed that the front electron current density in the O/N/F structureincreased by 2.8 times compared to the O/N/O structure, and the front electron current density ratio of the O/N/Fstructure was 17.7% higher. Therefore, the front current path is formed more effectively in the O/N/F structurethan in the O/N/O structure.

참고문헌 (15)

  1. Jae-Min Sim, "A New Read Scheme for Alleviating Cell-to-Cell Interference in Scaled-Down 3D NAND Flash Memory", Electronics, 9(11), pp.1775~ (2020), MDPI AG[DOI]
  2. Mincheol Park, "Direct Field Effect of Neighboring Cell Transistor on Cell-to-Cell Interference of nand Flash Cell Arrays", IEEE Electron Device Letters, 30(2), pp.174~177 (2009), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
  3. Ki-Tae Park, "A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories", IEEE Journal of Solid-State Circuits, 43(4), pp.919~928 (2008), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
  4. Giuk Kim, "High performance ferroelectric field-effect transistors for large memory-window, high-reliability, high-speed 3D vertical NAND flash memory", Journal of Materials Chemistry C, 10(26), pp.9802~9812 (2022), Royal Society of Chemistry (RSC)[DOI]
  5. Sangwoo Han, "Investigation of Inhibited Channel Potential of 3D NAND Flash Memory According to Word-Line Location", Electronics, 9(2), pp.268~ (2020), MDPI AG[DOI]
  6. Beomsu Kim, "Optimal Bias Condition of Dummy WL for Sub-Block GIDL Erase Operation in 3D NAND Flash Memory", Electronics, 11(17), pp.2738~ (2022), MDPI AG[DOI]
  7. Cristian Zambelli, "First Evidence of Temporary Read Errors in TLC 3D-NAND Flash Memories Exiting From an Idle State", IEEE Journal of the Electron Devices Society, 8, pp.99~104 (2020), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
  8. Dokyun Son, "Investigation and Compact Modeling of Hot-Carrier Injection for Read Disturbance in 3-D NAND Flash Memory", IEEE Transactions on Electron Devices, 67(7), pp.2778~2784 (2020), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
  9. Ilsik Ham, "Ferroelectric Polarization Aided Low Voltage Operation of 3D NAND Flash Memories", Electronics, 10(1), pp.38~ (2020), MDPI AG[DOI]
  10. 이재우, "Tapering과 Ferroelectric Polarization에 의한 3D NAND Flash Memory의 Lateral Charge Migration 분석", 전기전자학회논문지, 25(4), pp.770~773 (2021), 한국전기전자학회
  11. Seonjun Choi, "A Novel Structure to Improve the Erase Speed in 3D NAND Flash Memory to Which a Cell-On-Peri (COP) Structure and a Ferroelectric Memory Device Are Applied", Electronics, 11(13), pp.2038~ (2022), MDPI AG[DOI]
  12. Daewoong Kang, "Analysis of the current path for a vertical NAND flash cell with program", erase states, 2016, pp.31(3), 035011~[DOI]
  13. J. Kim, "Modeling of Channel Current in Sub-threshold Region for Poly-Si based Macaroni Structure in 3D NAND Flash Memories", Electron Devices Technology and Manufacturing Conference (EDTM), pp.200~202 (2019)
  14. Donghyun Ryu, "Investigation of Gate Sidewall Spacer Optimization From OFF-State Leakage Current Perspective in 3-nm Node Device", IEEE Transactions on Electron Devices, 66(6), pp.2532~2537 (2019), Institute of Electrical and Electronics Engineers (IEEE)[DOI]
  15. Jae-Min Sim, "A Novel Program Operation Scheme With Negative Bias in 3-D NAND Flash Memory", IEEE Transactions on Electron Devices, 68(12), pp.6112~6117 (2021), Institute of Electrical and Electronics Engineers (IEEE)[DOI]

관련 논문AI추천

이 간행물의 다른 논문 (42건)