Current Spreading Layer를 도입한 4.5 kV 4H-SiC MOSFET의 설계 및 최적화
Design and Optimization of 4.5 kV 4H-SiC MOSFET with Current Spreading Layer
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초록
이번 연구에서 우리는 낮은 온 저항을 위해 p-well 영역 아래에 도입된 전류 확산층을 변화시켜 고전압 4H-SiC 전력 DiffusedMOSFET (DMOSFET) 에 대해 연구했다. Current Spreading Layer (CSL)의 두께 (TCSL)를 0~0.9 um, CSL의 도핑 농도 (NCSL)를 1~5×1016 cm-3 으로 변화시키면서 소자의 전기적 특성을 분석하였다. TCAD 2D-simulation을 통해 최적화되었으며 CSL이온 저항을 낮추는 것뿐만 아니라 항복전압도 낮춤으로써 CSL의 최적화의 중요성을 확인하였다. 최적화된 구조는 59.61 mΩ·cm2의 온저항, 5 kV의 항복전압, 0.43 GW/cm2의 Baliga’s Figure of Merit (BFOM)을 보여주었다.
Abstract
In this work, we investigated a high-voltage (~4.5 kV) 4H—SiC power DMOSFET with modifications of currentspreading layer (CSL), which was introduced below the p-well region for low on-resistance. These include thefollowing: 1) a thickness of CSL (TCSL) from 0 um to 0.9 um; 2) a doping concentration of CSL (NCSL) from 1×1016cm-3 to 5×1016 cm-3. The design is optimized using TCAD 2D-simulation, and we found that CSL helps to reducespecific on-resistance but also breakdown voltage. The resulting structures exhibit a specific on-resistance (Ron,sp)of 59.61 mΩ·cm2, a breakdown voltage (VB) of 5 kV, and a Baliga’s Figure of Merit (BFOM) of 0.43 GW/cm2.
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