nT Pairing 알고리즘의 효율적인 하드웨어 구현
Efficient Hardware Implementation of nT Pairing Based Cryptography
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Recently in the field of the wireless sensor network, many researchers are attracted to pairing cryptography since it has ability to distribute keys without additive communication. In this paper, we propose efficient hardware implementation of pairing which is one of various pairing scheme. we suggest efficient hardware architecture of pairing based on parallel processing and register/resource optimization, and then we present the result of our FPGA implementation over . Our implementation gives 15% better result than others in Area Time Product.
Abstract
Recently in the field of the wireless sensor network, many researchers are attracted to pairing cryptography since it has ability to distribute keys without additive communication. In this paper, we propose efficient hardware implementation of pairing which is one of various pairing scheme. we suggest efficient hardware architecture of pairing based on parallel processing and register/resource optimization, and then we present the result of our FPGA implementation over . Our implementation gives 15% better result than others in Area Time Product.
참고문헌 (25)
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