구조를 고려한 CPLD 저전력 알고리즘
A CPLD Low Power Algorithm considering the Structure
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초록
In this paper, we propose a CPLD low power algorithm considering the structure. The proposed algorithm is implemented CPLD circuit FC(Feasible Cluster) for generating aproblem occurs when the node being split to overcome the area and power consumption canreduce the algorithm. CPLD to configure and limitations of the LE is that the number ofOR-terms. FC consists of an OR node is divided into mainly as a way to reduce the powerconsumption with the highest number of output nodes is divided into a top priority. Thehighest number of output nodes with the highest number of switching nodes become acut-point. Division of the node is the number of OR-terms of the number of OR-terms LE isgreater than adding the input and output of the inverter converts the AND. Reduce thelevel, power consumption and area. The proposed algorithm to MCNC logic circuits by applying a synthetic benchmarkexperimental results of 13% compared to the number of logical blocks decreased. 8% of thepower consumption results in a reduced efficiency of the algorithm represented been demonstrated.
Abstract
In this paper, we propose a CPLD low power algorithm considering the structure. The proposed algorithm is implemented CPLD circuit FC(Feasible Cluster) for generating aproblem occurs when the node being split to overcome the area and power consumption canreduce the algorithm. CPLD to configure and limitations of the LE is that the number ofOR-terms. FC consists of an OR node is divided into mainly as a way to reduce the powerconsumption with the highest number of output nodes is divided into a top priority. Thehighest number of output nodes with the highest number of switching nodes become acut-point. Division of the node is the number of OR-terms of the number of OR-terms LE isgreater than adding the input and output of the inverter converts the AND. Reduce thelevel, power consumption and area. The proposed algorithm to MCNC logic circuits by applying a synthetic benchmarkexperimental results of 13% compared to the number of logical blocks decreased. 8% of thepower consumption results in a reduced efficiency of the algorithm represented been demonstrated.
참고문헌 (10)
- "The Altera Data Book" (1996), Altera Corporation
- 김재진, "시간제약 조건하에서 면적을 고려한 LE로 구성된 CPLD 기술 매핑", 한국정보기술학회논문지, 6(3), pp.149~155 (2008), 한국정보기술학회
- SIS : A system for sequential Circuit Synthesis, "E. M. Sentovice", Electronics Research Laboratory, Department of Electrical Engineering and Computer Science, University of California, ~, pp.Technical Report UCM (1992), ERL M92[DOI]
- Jason Helge Anderson, "Technology Mapping for Large Complex PLDs", Design Automation Conference, pp.698~703 (1998)
- 윤충모, "시간적 조건에서 실행 시간을개선한 CPLD 기술 매핑 알고리즘 개발", 한국OA 학회 논문집, 4(3), pp.35~46 (1999), 한국OA 학회
- Jae-Jin Kim, "A New Technology Mapping for CPLD under the time constraint", ASP-DAC, pp.235~238 (2001)
- 김재진, "상관관계에 의한 CLB구조의 CPLD저전력 기술 매핑 알고리즘", 한국컴퓨터정보학회논문지, 10(2), pp.49~58 (2005), 한국컴퓨터정보학회
- 김재진, "시간제약 조건하에서 모듈 선택 재사용을 이용한 CPLD 저전력 기술 매핑", 한국컴퓨터정보학회논문지, 11(3), pp.161~166 (2006), 한국컴퓨터정보학회
- 김재진, "제한조건을 고려한 효율적 회로 설계 알고리즘", (사)디지털산업정보학회 논문지, 8(1), pp.41~46 (2012), (사)디지털산업정보학회
- 김재진, "배터리 잔량과 태스크에 따른 저전력 알고리즘 연구", (사)디지털산업정보학회 논문지, 9(1), pp.53~58 (2013), (사)디지털산업정보학회