시간제약 조건하에서 재사용 모듈 설계를 통한 CPLD 저전력 기술 매핑
CPLD Low Power Technology Mapping for Reuse Module Design under the Time Constraint
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Abstract
In this paper, CPLD low power technology mapping for reuse module design under the time constraint is proposed. Traditional high-level synthesis do not allow reuse of complex, realistic datapath component during the task of scheduling. On the other hand, the proposed algorithm is able to approach a productivity of the design the low power to reuse which given a library of user-defined datapath component and to share of resource sharing on the switching activity in a shared resource. Also, we are obtainable the optimal the scheduling result in experimental results of our using chaining and multi-cycling in the scheduling techniques. Low power circuit make using CPLD technology mapping algorithm for selection reuse module by scheduling.
참고문헌 (13)
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