22.5–27GHz High Suppression Frequency Tripler with Excellent Output Power Flatness in 65nm CMOS
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This paper presents a high harmonic suppression frequency tripler with an excellent output power flatness in 65nm CMOS process. In order to achieve a high first, second and forth harmonic suppression, the highly balanced different transformer is employed. The proposed tripler multiplies 7.5 - 9GHz to 22.5 - 27GHz with ±1.5-dB ripple. It suppresses the harmonic up to 40-dBc and consumes a DC power of 20 mW at a maximum operating point. The tripler occupies a 0.259 × 0.742 mm2.
Abstract
This paper presents a high harmonic suppression frequency tripler with an excellent output power flatness in 65nm CMOS process. In order to achieve a high first, second and forth harmonic suppression, the highly balanced different transformer is employed. The proposed tripler multiplies 7.5 - 9GHz to 22.5 - 27GHz with ±1.5-dB ripple. It suppresses the harmonic up to 40-dBc and consumes a DC power of 20 mW at a maximum operating point. The tripler occupies a 0.259 × 0.742 mm2.
참고문헌 (7)
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