A Method for Reducing the Number of Metal Layers for Embedded LSI Package
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초록
We have successfully demonstrated a high-pin-count and thin embedded-LSI package to realize next generation's mobile terminals. The following three design key points were applied: (i) Using Cu posts, (ii) Using the coreless structure, (iii) Using a Cu plate as the ground plane. In order to quantitatively determine the contribution of the three points, the five-stage process for reducing the number of metal layers is described by means of the electrical simulation. The point-(i) and (ii) are effective from the viewpoint of the power integrity (PI); that is, these points play important roles in reducing the number of metal layers, and especially the point-(ii) contributes at least twice as the point-(i). The point-(iii) is not effective in the PI, but has a few effects on the signal integrity (SI). For reducing the number of metal layers, we should, at first, pay attention whether the PI characteristics fulfill the specification, and then we should confirm the SI characteristics.
Abstract
We have successfully demonstrated a high-pin-count and thin embedded-LSI package to realize next generation's mobile terminals. The following three design key points were applied: (i) Using Cu posts, (ii) Using the coreless structure, (iii) Using a Cu plate as the ground plane. In order to quantitatively determine the contribution of the three points, the five-stage process for reducing the number of metal layers is described by means of the electrical simulation. The point-(i) and (ii) are effective from the viewpoint of the power integrity (PI); that is, these points play important roles in reducing the number of metal layers, and especially the point-(ii) contributes at least twice as the point-(i). The point-(iii) is not effective in the PI, but has a few effects on the signal integrity (SI). For reducing the number of metal layers, we should, at first, pay attention whether the PI characteristics fulfill the specification, and then we should confirm the SI characteristics.
참고문헌 (3)
- K. Mori, "A Novel Ultra-thin Package for Embedded High-pin-count LSI Supported by Cu Plate", Proc. 59th Electronic Components and Technology Conference (ECTC), pp.1447~ (2009), IEEE Components, Packaging and Manufacturing Technology Society (CPMT)
- D. Ohshima, "Electrical Design and Demonstration of an Embedded High-pin-count LSI Chip Package", Proc. 59th Electronic Components and Technology Conference (ECTC), pp.482~ (2009), IEEE Components, Packaging and Manufacturing Technology Society (CPMT)
- J. Sakai, "Signal Integrity and Power Integrity Properties of FCBGA Based on Ultra-Thin, High-density Package Substrate", Proc. 55th Electronic Components and Technology Conference (ECTC), Lake Buena Vista, pp.284~ (2005), IEEE Components, Packaging and Manufacturing Technology Society (CPMT)