Selecting a Synthesizable RISC-V Processor Core for Low-cost Hardware Devices
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The Internet-of-Things (IoT) has been deployed in almost every facet of our day to day activities. This is madepossible because sensing and data collection devices have been given computing and communicationcapabilities. The devices implement System-on-Chips (SoCs) that incorporate a lot of functionalities, yet theyare severely constrained in terms of memory capacitance, hardware area, and power consumption. With theincrease in the functionalities of sensing devices, there is a need for low-cost synthesizable processors to handlecontrol, interfacing, and error processing. The first step in selecting a synthesizable processor core for low-costdevices is to examine the hardware resource utilization to make sure that it fulfills the requirements of thedevice. This paper gives an analysis of the hardware resource usage of ten synthesizable processors thatimplement the Reduced Instruction Set Computer Five (RISC-V) Instruction Set Architecture (ISA). All theten processors are synthesized using Vivado v2018.02. The maximum frequency, area, and power reports areextracted and a comparison is made to determine which processor is ideal for low-cost hardware devices.
Abstract
The Internet-of-Things (IoT) has been deployed in almost every facet of our day to day activities. This is madepossible because sensing and data collection devices have been given computing and communicationcapabilities. The devices implement System-on-Chips (SoCs) that incorporate a lot of functionalities, yet theyare severely constrained in terms of memory capacitance, hardware area, and power consumption. With theincrease in the functionalities of sensing devices, there is a need for low-cost synthesizable processors to handlecontrol, interfacing, and error processing. The first step in selecting a synthesizable processor core for low-costdevices is to examine the hardware resource utilization to make sure that it fulfills the requirements of thedevice. This paper gives an analysis of the hardware resource usage of ten synthesizable processors thatimplement the Reduced Instruction Set Computer Five (RISC-V) Instruction Set Architecture (ISA). All theten processors are synthesized using Vivado v2018.02. The maximum frequency, area, and power reports areextracted and a comparison is made to determine which processor is ideal for low-cost hardware devices.
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