STP-FTL: 요구 기반의 플래시 변환 계층을 위한 효율적인 캐싱 구조
STP-FTL: An Efficient Caching Structure for Demand-based Flash Translation Layer
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초록
As the capacity of NAND flash module increases, the amount of RAM increases for caching and maintaining the FTL mapping information. In order to reduce the amount of mapping information managed in the RAM, a demand-based address mapping method stores the entire mapping information in the flash and some valid mapping information in the form of cache in the RAM so that the RAM can be used efficiently. However, when cache miss occurs, it is necessary to read the mapping information recorded in the flash, so overhead occurs to translate the address. If the RAM space is not enough, the cache hit ratio decreases, resulting in greater overhead. In this paper, we propose a method using two tables called TPMT(Translation Page Mapping Table) and SMT(Segmented Translation Page Mapping Table) to utilize both temporal locality and spatial locality more efficiently. A performance evaluation shows that this method can improve the cache hit ratio by up to 30% and reduces the extra translation operations by up to 72%, compared to the TPM scheme.
Abstract
As the capacity of NAND flash module increases, the amount of RAM increases for caching and maintaining the FTL mapping information. In order to reduce the amount of mapping information managed in the RAM, a demand-based address mapping method stores the entire mapping information in the flash and some valid mapping information in the form of cache in the RAM so that the RAM can be used efficiently. However, when cache miss occurs, it is necessary to read the mapping information recorded in the flash, so overhead occurs to translate the address. If the RAM space is not enough, the cache hit ratio decreases, resulting in greater overhead. In this paper, we propose a method using two tables called TPMT(Translation Page Mapping Table) and SMT(Segmented Translation Page Mapping Table) to utilize both temporal locality and spatial locality more efficiently. A performance evaluation shows that this method can improve the cache hit ratio by up to 30% and reduces the extra translation operations by up to 72%, compared to the TPM scheme.
참고문헌 (11)
- S. Lee, "A log buffer based flash tarnslation layer using fully associative sector translation", ACM Trans. Embedded Computing Sys, 6(3), pp.1~27 (2007)
- GUPTA, A, "DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings", Proceedings of ASPLOS’09, pp.229~240 (2009)
- Zhiwei Qin, "A Two-Level Caching Mechanism for Demand-Based Page-Level Address Mapping in NAND Flash Memory Storage Systems", Proceedings of the 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium, pp.157~166 (2011)
- Qi Zhang, "Optimizing translation information management in NAND flash memory storage systems", Proceedings of the 18th Asia and South Pacific Design Automation Conference (ASP-DAC'13), pp.326~331 (2013)
- "Yet another flash file system"[URL]
- "JFFS3 design issues"[URL]
- C. Lee, "F2FS: A New File System for Flash Storage", Proc. 13th USENIX Conference on File and Storage Technologies (FAST'15), pp.273~286 (2015)
- "OLTP Trace from UMass Trace Repository"[URL]
- "Websearch Trace from Umass Trace Repository"[URL]
- Z. Qin., "MNFTL: an efficient flash translation layer for MLC NAND flash memory storage systems", DAC '11, pp.17~22 (2011)
- You Zhou, "An efficient page-level FTL to optimize address translation in flash memory", Proceedings of the Tenth European Conference on Computer Systems (2015)