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NAND 플래시 메모리 저장장치를 위한 시간적 지역성과 공간적 지역성을 고려한 효율적인 플래시 변환 계층

An Efficient Flash Translation Layer Considering Temporal and Spacial Localities for NAND Flash Memory Storage Systems

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주제분류컴퓨터학

초록

This paper presents an efficient FTL for NAND flash based SSDs. Address translation information of page mapping based FTLs is stored on flash memory pages and address translation cache keeps frequently accessed entries. The proposed FTL of this paper reduces response time by considering both of temporal and spacial localities of page access patterns in translation cache management. The localities of several well-known traces are evaluated and determine the structure of the cache for high hit ratio. A simulation with several well-known traces shows that the presented FTL reduces response time in comparison to previous FTLs and can be used with relatively small size of caches.

Abstract

This paper presents an efficient FTL for NAND flash based SSDs. Address translation information of page mapping based FTLs is stored on flash memory pages and address translation cache keeps frequently accessed entries. The proposed FTL of this paper reduces response time by considering both of temporal and spacial localities of page access patterns in translation cache management. The localities of several well-known traces are evaluated and determine the structure of the cache for high hit ratio. A simulation with several well-known traces shows that the presented FTL reduces response time in comparison to previous FTLs and can be used with relatively small size of caches.

참고문헌 (11)

  1. A. Gupta, "DFTL: A Flash Translation Layer Employing Demand-Based Selective Caching of Page-Level Address Mappings", Proc. 14th Int. Conf. Archit. Support Program. Languages Operating Syst, pp.229~240 (2009)
  2. J. Kim, "A Space Efficient Flash Translation Layer for CompactFlash System", IEEE Trans. Consum. Electron, 48(2), pp.366~375 (2002)
  3. S.-W. Lee, "Log Buffer-Based Flash Translation Layer Using Fully-Associative Sector Translation", ACM Trans. Emb. Comput. Syst, 6(3), pp.1~27 (2007)
  4. Y. Guan, "A Block-Level Log-Block Management Scheme for MLC NAND Flash Memory Storage Systems", IEEE Trans. on Computers, 66(9) (2017)
  5. Y. Zhou, "An Efficient Page-level FTL to Optimize Address Translation in Flash Memory", Proc. 10th European Conference on Computer Systems (2015)
  6. Z. W. Qin, "A Two-Level Caching Mechanism for Demand-Based Page-Level Address Mapping in NAND Flash Memory Storage Systems", Proc. of the 17th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp.157~166 (2011)
  7. S. Jiang, "S-FTL: An Efficient Address Translation for Flash Memory by Exploiting Spatial Locality", Proc. of Mass Storage Systems and Technologies (MSST) (2011)
  8. 최환필, "대용량 플래시 메모리 드라이브를 위한 효율적인 플래시 변환계층 캐시 관리 방안", 한국컴퓨터정보학회논문지, 20(11), pp.31~38 (2015), 한국컴퓨터정보학회
  9. 최환필, "STP-FTL: An Efficient Caching Structure for Demand-based Flash Translation Layer", 한국컴퓨터정보학회논문지, 22(7), pp.1~7 (2017), 한국컴퓨터정보학회
  10. "Storage Traces of UMass Trace Repository"[URL]
  11. "Samsung 1G x 8 Bit - 2G x 8 Bit- 4G x 8 Bit NAND Flash Memory Datasheet (K9XXG08UXA)"[URL]

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