Implementation of a DBPSK/DQPSK DSSS MODEM ASIC Chip
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This paper presents a high-speed DSSS MODEM ASIC chip for wireless local area network (WLAN). The implemented MODEM chip supports the DSSS physical layer specifications of the IEEE 802.11. The chip supports various data rates, i.e., 4Mbps, 2Mbps and 1Mbps and provides both DBPSK and DQPSK for data modulation. We have simulated algorithm models using the SPWTM and verified the BER performance in AWGN channel environments. Moreover, we have verified the BER performance for the carrier frequency offset and clock offset under the AWGN channel environments. We have simulated the architecture using VHDL models and have performed logic synthesis using the SYNOPSYSTM (v3.4a) Design Analyzer. The chip has been fabricated using the 0.6μm gate array library (KG75), consists of 53,355 gates and operates at 44MHz. The implemented architecture shows lower BER than the Harris HSP3824.
Abstract
This paper presents a high-speed DSSS MODEM ASIC chip for wireless local area network (WLAN). The implemented MODEM chip supports the DSSS physical layer specifications of the IEEE 802.11. The chip supports various data rates, i.e., 4Mbps, 2Mbps and 1Mbps and provides both DBPSK and DQPSK for data modulation. We have simulated algorithm models using the SPWTM and verified the BER performance in AWGN channel environments. Moreover, we have verified the BER performance for the carrier frequency offset and clock offset under the AWGN channel environments. We have simulated the architecture using VHDL models and have performed logic synthesis using the SYNOPSYSTM (v3.4a) Design Analyzer. The chip has been fabricated using the 0.6μm gate array library (KG75), consists of 53,355 gates and operates at 44MHz. The implemented architecture shows lower BER than the Harris HSP3824.