Design of A Grand Alliance VSB HDTV Demodulator
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In this paper, we describe the design and hardware test results of a demodulator satisfying the US Grand-Alliance VSB HDTV standard. Novel algorithms that offer satisfactory performance with efficient hardware implementation are developed and employed in the prototype hardware. Satisfactory performance of the implemented prototype was verified and the demodulator is currently in the ASIC fabrication stage. Main algorithms of interest in this paper are the segmentation and symbol timing synchronization, FPLL polarity detection and compensation, phase/gain tracking loops and channel equalization.
Abstract
In this paper, we describe the design and hardware test results of a demodulator satisfying the US Grand-Alliance VSB HDTV standard. Novel algorithms that offer satisfactory performance with efficient hardware implementation are developed and employed in the prototype hardware. Satisfactory performance of the implemented prototype was verified and the demodulator is currently in the ASIC fabrication stage. Main algorithms of interest in this paper are the segmentation and symbol timing synchronization, FPLL polarity detection and compensation, phase/gain tracking loops and channel equalization.