저전력 BLE/ZigBee IoT MCU 용 RF transciever 설계 연구
A Study on Low Power RF Transceiver Design for BLE / ZigBee IoT MCU Chip
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초록
최근 저전력 센서 네트워크에 대한 관심이 급속히 증가하면서 BLE/ZigBee IoT MCU 용 RF transceiver 설계가 매우 중요한 과제가 되었다. 본 논문에서는 Bluetooth 5.0 core spec과 IEEE 802.15.4 ZigBee spec을 검토한 후 최적의 저전력 저가 IoT MCU 칩 구현을 위한 RF transceiver architecture를 제안하였다. 본 논문에서는 높은 dynamic range를 갖는 ADC와 digital filter를 포함한 low-IF 수신기 구조를 제안하였다. 제안된 구조는 analog filter를 사용하지 않아 전력 소모와 칩 면적을 동시에 개선할 수 있는 장점이 있다. 또 low-IF 수신기의 특성으로 인해 DC offset 제거를 위한 high pass filter를 제거하여 칩 면적 개선 및 DC offset 제거와 flicker noise로 인한 성능 열화를 개선하였다. 송신기는 two pint modulation과 크기 위상 보상 기법을 포함한 direct frequency modulation 구조를 제안하였으며, 5bit binary-weighted inverse class-F 전력 증폭기를 제안하였다. Inverse class-F 전력 증폭기는 class-F 전력 증폭기보다 개선된 전력 효율 특성을 보이며, 5bit binary-weighted 된 트랜지스터는 최대 출력 전력의 조절 및 출력 전력 ramping에 사용된다. 또 FCC의 spurious emission 요구 규격을 만족하기 위해 on-chip 및 off-chip 필터링 기법과 LO duty ratio를 보정하여 3차 및 2차 고조파를 억압하는 방법을 제안하였다. 마지막으로 본 논문에서는 배터리 사용 상황과 고정 전원 사용 상황을 모두 지원하여 저전력과 BOM cost 최적화를 달성하기 위해 buck과 global LDO를 사용하는 power architecture를 제안하였으며, 본 논문에서 제안된 RF transceiver 및 power architecture를 사용함으로 인해 저전력 및 고성능을 동시에 달성할 수 있다.
Abstract
Recently, the demand of BLE/ZigBee IoT MCU is highly increased for low power sensor network realization. In this paper, a low power and low cost BLE/ZigBee RF transceiver is studied with careful review of Bluetooth 5.0 core specification for BLE and IEEE 802.15.4 ZigBee specification. For the receiver side, a low-IF architecture with digital filtering and high ADC dynamic range is used to eliminate the analog filter to achieve both of small size and low power consumption simultaneously. Thanks to the inherent characteristics of a low-IF receiver, the proposed architecture also has the merits of high performance because of no signal loss due to DC offset removal filter and no flicker noise. For the transmitter side, a direct frequency modulation based on two point modulation and gain and phase mismatch calibration is proposed also for low power consumption. Moreover, 5bit binary-weighted inverse class-F power amplifier is proposed because the inverse class-F power amplifier shows greatly improved power efficiency even better than that of the class-F power amplifier. The 5bit binary-weighting is used for maximum transmit output power control as well as transmitter ramping for on-to-off and off-to-on transition. To meet FCC spurious emission regulation, on-chip and off-chip LC filtering and LO duty ratio control to suppress 3rd harmonic and 2nd harmonic, respectively. Finally, this paper presents the power architecture, which can support battery operation and solid power supply operation for best power efficiency and BOM cost optimization.
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