듀티 사이클 보정이 가능한 멀티 클럭 제너레이터
Multi-Clock Generator with Duty-Cycle Correction
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참고문헌
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초록
본 논문에서는 고속 Soc 설계시 필요한 클록킹 회로의 핵심 기술인 클록 듀티 보정 회로(Duty-Cycle Corrector: DCC)에 대해서 설명한다. 즉, 기존 논-피드백 DCC의 문제점인 XOR의 미스매치와 초기값에 의한 위상반전 문제를 설명하고, 이를 보완하는 새로운 구조의 논-피드백 DCC 회로를 제안하였다. 제안된 DCC회로는 기존 논-피드백 DCC 대비 더 적은 회로면적을 사용하는 장점을 갖는다.
Abstract
In this paper, we introduce the clock duty correction circuit (DCC), which is a core technology of the clocking circuit required for high-speed SoC. The problem of the conventional non feedback DCC which has mismatch of the XOR and the phase inversion by the initial value is explained, and a new structure of the non feedback DCC circuit is proposed. The proposed DCC circuit has the advantage of using less circuit area compared to the conventional non feedback DCC circuit.
참고문헌 (6)
- S. K. Kao, "All-Digital Fast-Locked Synchronous Duty-Cycle Corrector", IEEE Trans. on Circuits and Systems, 53, pp.1363~1367 (2006)
- B. Kim, "A 500MHz DLL with Second Order Duty Cycle Corrector for Low Jitter", IEEE Custom Integrated Circuits Conference, pp.325~328 (2005)
- J. C. Ha, "Unified all-digital duty cycle and phase correction circuit for QDR I", O interface, 2008, 1300~1301
- S. Han, "Hybrid duty-cycle corrector circuit with dual feedback loop", IET Electronics Letters, 47(24), pp.1311~1313 (2011)
- Chan-Hui Jeong, "All-Digital Duty-Cycle Corrector With a Wide Duty Correction Range for DRAM Applications", Very Large Scale Integration (VLSI) Systems IEEE Transactions on, 24(1), pp.363~367 (2016)
- Young-Jae Min, ""A 0.31–1 GHz Fast-Corrected Duty-Cycle Corrector With Successive Approximation Register for DDR DRAM Applications", VLSI Systems IEEE Transactions on, 20(8), pp.1524~1528 (2012)