센서네트워크 활용을 위한 경량 병렬 BCH 디코더 설계
Design of Lightweight Parallel BCH Decoder for Sensor Network
1
조회
0
다운로드
1
인용
0
참고문헌
키워드
초록
This paper presents a new byte-wise BCH (4122, 4096, 2) decoder, which treats byte-wise parallel operations so as to enhance its throughput. In particular, we evaluate the parallel processing technique for the most time-consuming components such as syndrome generator and Chien search owing to the iterative operations. Even though a syndrome generator is based on the conventional LFSR architecture, it allows eight consecutive bit inputs in parallel and it treats them in a cycle. Thus, it can reduce the number of cycles that are needed. In addition, a Chien search eliminates the redundant operations to reduce the hardware complexity. The proposed BCH decoder is implemented with VHDL and it is verified using a Xilinx FPGA. From the simulation results, the proposed BCH decoder can enhance the throughput as 43% and it can reduce the hardware complexity as 67% compared to its counterpart employing parallel processing architecture.
Abstract
This paper presents a new byte-wise BCH (4122, 4096, 2) decoder, which treats byte-wise parallel operations so as to enhance its throughput. In particular, we evaluate the parallel processing technique for the most time-consuming components such as syndrome generator and Chien search owing to the iterative operations. Even though a syndrome generator is based on the conventional LFSR architecture, it allows eight consecutive bit inputs in parallel and it treats them in a cycle. Thus, it can reduce the number of cycles that are needed. In addition, a Chien search eliminates the redundant operations to reduce the hardware complexity. The proposed BCH decoder is implemented with VHDL and it is verified using a Xilinx FPGA. From the simulation results, the proposed BCH decoder can enhance the throughput as 43% and it can reduce the hardware complexity as 67% compared to its counterpart employing parallel processing architecture.
참고문헌 (9)
- S. Lin, "Error Control Coding" (2004), Prentice Hall
- R. Martin, "Fault detection and diagnosis for multilevel cell flash memories", Proc. of IMT 2006, pp.1896~1901 (2006)
- S. C. Jang, "Design of a parallel BCH decoder for MLC memory", Proc. ISOCC ’08, 3, pp.46~47 (2008)
- Chen, Yanni, "Small Area Parallel Chien Search Architectures for Long BCH Codes", IEEE Trans. Inform. Theory, 12(5), pp.545~549 (2004)
- Y. J. Lee, "Small-area parallel syndrome calculation for strong BCH decoding", Proc. of ICASSP 2012, pp.1609~1612 (2012)
- Massey, J, L., "Shift-register synthesis and BCH decoding", IEEE Trans. Inform. Theory, 15(1), pp.122~127 (1969)
- J. H. Jeng, "On decoding of both errors and erasures of a Reed-Solomon code using an inverse-free Berlekamp-Massey algorithm", IEEE Trans. Commun, 47(10), pp.1488~1494 (1999)
- R. T. Chien, "Cyclic decoding procedure for the Bose-Chaudguri-Hocquenhem Code", IEEE Trans. Inform. Theory, 10(10), pp.357~363 (1964)
- S. V. Fedorenko, "Finding roots of polynomials over finite fields", IEEE Trans. Commun., 50(11) (2002)