Algorithm of Modified Single-slope A/D Converter with Improved Conversion Time for CMOS Image Sensor System
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This paper proposes an algorithm that reduces the conversion time of a single-slope A/D converter (SSADC) that has nbit resolution, which typically is limited by conversion time taking up to 2n clock cycles for an operation. To improve this situation, we have researched a novel hybrid-type A/D converter that consists of a pseudo-pipeline A/D converter and a conventional SSADC. The pseudo-pipeline A/D converter, using a single-stage of analog components, determines the most significant bits (MSBs) or upper bits and the conventional SSADC determines the remaining bits. Therefore, the modified SSADC, similar to the hybrid-type A/D converter, is able to significantly reduce the conversion time because the pseudopipeline A/D converter, which determines the MSBs (or upper bits), does not rely on a clock. The proposed A/D converter was designed using a 0.35-μm 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) technology process; additionally, its characteristics were simulated.
Abstract
This paper proposes an algorithm that reduces the conversion time of a single-slope A/D converter (SSADC) that has nbit resolution, which typically is limited by conversion time taking up to 2n clock cycles for an operation. To improve this situation, we have researched a novel hybrid-type A/D converter that consists of a pseudo-pipeline A/D converter and a conventional SSADC. The pseudo-pipeline A/D converter, using a single-stage of analog components, determines the most significant bits (MSBs) or upper bits and the conventional SSADC determines the remaining bits. Therefore, the modified SSADC, similar to the hybrid-type A/D converter, is able to significantly reduce the conversion time because the pseudopipeline A/D converter, which determines the MSBs (or upper bits), does not rely on a clock. The proposed A/D converter was designed using a 0.35-μm 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) technology process; additionally, its characteristics were simulated.
참고문헌 (8)
- M. Shin, "Column parallel single-slope ADC with time to digital converter for CMOS imager", Proc. IEEE Conf. Electronics, Circuits, and Systems, pp.863~866 (2010)
- S. Lim, "A hige-speed CMOS image sensor with column-parallel two-step single-slope ADCs", IEEE Transactions on Electron Devices, 56(3), pp.393~398 (2009)
- A. Mahdy, "A high-speed analog comparator in 0.5 μm CMOS technology", National Radio Science Conference NRSC 2008, pp.1~7 (2008)
- M. J. Cabebe, "Design tradeoffs in a 0. 5 V 65 nm CMOS folded cascade OTA", IEEE TENCON Spring Conf, 2013, pp.293~297 (2013)
- C. H. Kuo, "Bias-and-input interchanging technique for cyclic", pipelined ADCs with opamp sharing, 2010, pp.57(3), 168~172
- V. Coelho, "A high-swing MOS cascade bias circuit", IEEE Transactions on Circuits and Systems II, 47(11), pp.1325~1328 (2000)
- I. Y. Oh, "Dynamic bias circuit of CMOS power amplifier sensing dissipated signals", IET Electronics Letters, 45(14), pp.744~746 (2009)
- K. B Klaassen, "A fast and unilateral monolithic switch for analog signals", IEEE Journal of Solid-State Circuits, 13(2), pp.258~261 (1978)