Low-Power CMOS image sensor with multi-column-parallel SAR ADC
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초록
This work presents a low-power CMOS image sensor (CIS) with a multi-column-parallel (MCP) readout structure while focusing on improving its performance compared to previous works. A delta readout scheme that utilizes the image characteristics is optimized for the MCP readout structure. By simply alternating the MCP readout direction for each row selection, additional memory for the rowto-row delta readout is not required, resulting in a reduced area of occupation compared to the previous work. In addition, the bias current of a pre-amplifier in a successive approximate register (SAR) analog-to-digital converter (ADC) changes according to the operating period to improve the power efficiency. The prototype CIS chip was fabricated using a 0.18-µm CMOS process. A 160 × 120 pixel array with 4.4 µm pitch was implemented with a 10-bit SAR ADC. The prototype CIS demonstrated a frame rate of 120 fps with a total power consumption of 1.92 mW.
Abstract
This work presents a low-power CMOS image sensor (CIS) with a multi-column-parallel (MCP) readout structure while focusing on improving its performance compared to previous works. A delta readout scheme that utilizes the image characteristics is optimized for the MCP readout structure. By simply alternating the MCP readout direction for each row selection, additional memory for the rowto-row delta readout is not required, resulting in a reduced area of occupation compared to the previous work. In addition, the bias current of a pre-amplifier in a successive approximate register (SAR) analog-to-digital converter (ADC) changes according to the operating period to improve the power efficiency. The prototype CIS chip was fabricated using a 0.18-µm CMOS process. A 160 × 120 pixel array with 4.4 µm pitch was implemented with a 10-bit SAR ADC. The prototype CIS demonstrated a frame rate of 120 fps with a total power consumption of 1.92 mW.
참고문헌 (18)
- M. Amjad, "Wireless multimedia cognitive radio networks : A comprehensive survey", IEEE Commun. Surveys Tut., 20(2), pp.1056~1103 (2018)
- H. Kim, "11-bit Column-Parallel Single-Slope ADC With First-Step Half-Reference Ramping Scheme for High-Speed CMOS Image Sensors", Journal of Solid-State Circuits, 56(7), pp.2132~2141 (2021)
- S. Sukegawa, "A 1", 4-inch 8 Mpixel backilluminated stacked CMOS image sensor, 2013, 484~485
- T. Arai, "6.9 A 1.1μm 33Mpixel 240fps 3D-stacked CMOS image sensor with 3-stage cyclic-based analog-todigital converters", IEEE Conf. International Solid-State Circuits, pp.126~128 (2016)
- C. Okada, "7.6 A High-Speed Back-Illuminated Stacked CMOS Image Sensor with Column-Parallel kT", CCancelling S&H and Delta-Sigma ADC, 2021, 116~118
- D. Van Blerkom, "Analysis of front-end multiplexing for column parallel image sensors", Proc. IEEE International Image Sensor Workshop, pp.1~4 (2011)
- H. J. Kim, "A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column Parallel SAR ADCs", Journal of Solid-State Circuits, 51(10), pp.2262~2273 (2016)
- H. J. Kim, "A Dual Imaging Speed-Enhanced CMOS Image Sensor for Real Time Edge Image Extraction", Journal of Solid-State Circuits, 52(9), pp.2488~2497 (2017)
- F. M. Yaul, "11.3 A 10b 0.6nW SAR ADC with data-dependent energy savings using LSBfirst successive approximation", IEEE ISSCC Dig. Tech. papers, pp.198~199 (2014)
- J. Yang, "A highly noise-immune touch controller using Filtered-Delta-Integration and a charge-interpolation technique for 10.1-inch capacitive touch-screen panels", IEEE Conf. International Solid-State Circuits, pp.390~391 (2012)
- R. Funatsu, "6. 2 133Mpixel 60fps CMOS image sensor with 32-column shared high-speed column-parallel SAR ADCs", IEEE Conf. International Solid-State Circuits, pp.112~113 (2015)
- E. Sanchez-Sinencio, "Operational transconductance amplifier-based nonlinear function syntheses", Journal of Solid-State Circuits, 24, pp.1576~1586 (1989)
- M. W. Seo, "A low noise wide dynamic range CMOS image sensor with low-noise transistors and 17b column-parallel ADCs", IEEE Sensors Journal, 13(8), pp.2992~2929 (2013)
- S. Kawahito, "Column readout circuit design for high speed low noise imaging", IEEE Conf. International Solid-State Circuits, Image Sensor Forum (2010)
- M. Kwon, "A New Figure of Merit Equation for Analog-to-Digital Converters in CMOS Image Sensors", International Symposium on Circuits and Systems (ISCAS), pp.1~5 (2018)
- D. G. Chen, "A Low-Power Pilot-DAC Based Column Parallel 8b SAR ADC With Forward Error Correction for CMOS Image Sensors", IEEE Transactions on Circuits and Systems I : Regular Papers, 60(10), pp.2572~2583 (2013)
- D. G. Chen, "A 64 fJ", step 9-bit SAR ADC Array With Forward Error Correction and Mixed-Signal CDS for CMOS Image Sensors, 2014, pp.61(11), 3085~3093