센서 시스템에서의 고신뢰 물리적 복제방지 기능의 저전력 칩 설계 및 구현
Design and Implementation of a Low Power Chip with Robust Physical Unclonable Functions on Sensor Systems
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Among Internet of things (IoT) applications, the most demanding requirements for the widespread realization of many IoT visions are security and low power. In terms of security, IoT applications include tasks that are rarely addressed before such as secure com-putation, trusted sensing, and communication, privacy, and so on. These tasks ask for new and better techniques for the protection ofdata, software, and hardware. An integral part of hardware cryptographic primitives are secret keys and unique IDs. Physical UnclonableFunctions(PUF) are a unique class of circuits that leverage the inherent variations in manufacturing process to create unique, unclonable IDs and secret keys. In this paper, we propose a low power Arbiter PUF circuit with low error rate and high reliability compared withconventional arbiter PUFs. The proposed PUF utilizes a power gating structure to save the power consumption in sleep mode, and usesa razor flip-flop to increase reliability. PUF has been designed and implemented using a FPGA and a ASIC chip (a 0.35 um technology). Experimental results show that our proposed PUF solves the metastability problem and reduce the power consumption of PUF com- pared to the conventional Arbiter PUF. It is expected that the proposed PUF can be used in systems required low power consumptionand high reliability such as low power encryption processors and low power biomedical systems.
Abstract
Among Internet of things (IoT) applications, the most demanding requirements for the widespread realization of many IoT visions are security and low power. In terms of security, IoT applications include tasks that are rarely addressed before such as secure com-putation, trusted sensing, and communication, privacy, and so on. These tasks ask for new and better techniques for the protection ofdata, software, and hardware. An integral part of hardware cryptographic primitives are secret keys and unique IDs. Physical UnclonableFunctions(PUF) are a unique class of circuits that leverage the inherent variations in manufacturing process to create unique, unclonable IDs and secret keys. In this paper, we propose a low power Arbiter PUF circuit with low error rate and high reliability compared withconventional arbiter PUFs. The proposed PUF utilizes a power gating structure to save the power consumption in sleep mode, and usesa razor flip-flop to increase reliability. PUF has been designed and implemented using a FPGA and a ASIC chip (a 0.35 um technology). Experimental results show that our proposed PUF solves the metastability problem and reduce the power consumption of PUF com- pared to the conventional Arbiter PUF. It is expected that the proposed PUF can be used in systems required low power consumptionand high reliability such as low power encryption processors and low power biomedical systems.
참고문헌 (8)
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