Floating Inverter Amplifiers with Enhanced Voltage Gains Employing Cross-Coupled Body Biasing
0
조회
0
다운로드
0
인용
0
참고문헌
키워드
초록
Floating inverter amplifiers (FIAs) have recently garnered considerable attention owing to their high energy efficiency and inherentresilience to input common-mode voltages and process-voltage-temperature variations. Since the voltage gain of a simple FIA is low,it is typically cascaded or cascoded to achieve a higher voltage gain. However, cascading poses stability concerns in closed-loop applications,while cascoding limits the output swing. This study introduces a gain-enhanced FIA that features cross-coupled body biasing. Through simulations, it is demonstrated that the proposed FIA designed using a 28-nm complementary metal-oxide-semiconductor technologywith a 1-V power supply can achieve a high voltage gain (> 90 dB) suitable for dynamic open-loop applications. The proposedFIA can also be used as a closed-loop amplifier by adjusting the amount of positive feedback due to the cross-coupled body biasing. The capability of achieving a high gain with minimum-length devices makes the proposed FIA a promising candidate for low-power,high-speed sensor interface systems.
Abstract
Floating inverter amplifiers (FIAs) have recently garnered considerable attention owing to their high energy efficiency and inherentresilience to input common-mode voltages and process-voltage-temperature variations. Since the voltage gain of a simple FIA is low,it is typically cascaded or cascoded to achieve a higher voltage gain. However, cascading poses stability concerns in closed-loop applications,while cascoding limits the output swing. This study introduces a gain-enhanced FIA that features cross-coupled body biasing. Through simulations, it is demonstrated that the proposed FIA designed using a 28-nm complementary metal-oxide-semiconductor technologywith a 1-V power supply can achieve a high voltage gain (> 90 dB) suitable for dynamic open-loop applications. The proposedFIA can also be used as a closed-loop amplifier by adjusting the amount of positive feedback due to the cross-coupled body biasing. The capability of achieving a high gain with minimum-length devices makes the proposed FIA a promising candidate for low-power,high-speed sensor interface systems.
참고문헌 (15)
- Y. Chae, "Low voltage, low power, inverterbased switched-capacitor Delta-Sigma modulator", IEEE J. Solid-State Circuits, 44(2), pp.458~472 (2009)
- W. Bae, "CMOS inverter as analog circuit : An overview", J. Low Power Electron. Appl., 9(3), pp.26(1)~26(15) (2019)
- J. Lin, "A 15.5 dB, wide signal swing, dynamic amplifier using a common-mode voltage detection technique", Proc. of 2011 IEEE Int. Symp. Circuits. Syst. (ISCAS), pp.21~24 (2011)
- F. V. D. Goes, "A 1. 5 mW 68 dB SNDR 80 MS", s 2x interleaved pipelined SAR ADC in 28 nm CMOS, 2014, pp.49(12), 2835~2845
- M. Zhang, "Gain?boosted dynamic amplifier for pipelined?SAR ADCs", Electron. Lett., 53(11), pp.708~709 (2017)
- C. -C. Liu, "28.1 A 0.46 mW 5MHz-BW 79.7 dB-SNDR noise-shaping SAR ADC with dynamic-amplifier-based FIR-IIR filter", Proc. of IEEE Int. Solid-State Circuits Conf. (ISSCC), pp.466~467 (2017)
- X. Tang, "An energy-efficient comparator with dynamic floating inverter pre-amplifier", Proc. of 2019 Symposium on VLSI Circuits, pp.C140~C141 (2019)
- X. Tang, "An energy-efficient comparator with dynamic floating inverter amplifier", IEEE J. Solid-State Circuits, 55(4), pp.1011~1022 (2020)
- X. Tang, "A 13. 5b-ENOB second-order noise-shaping SAR with PVT-robust closed-loop dynamic amplifier", Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), pp.162~163 (2020)
- X. Tang, "A 0. 4-to-40MS", s 75. 7 dB-SNDR fully dynamic event-driven pipelined ADC with 3-stage cascoded floating inverter amplifier, 2021, 376~377
- A. Matsuoka, "Fully dynamic discrete-time ΔΣ ADC using closed-loop two-stage cascoded floating inverter amplifiers", IEEE Trans. Circuits Syst. II : Express Briefs, 69(3), pp.944~948 (2021)
- H. Li, "Energy-efficient CMOS humidity sensors using adaptive range-shift zoom CDC and power-aware floating inverter amplifier array", IEEE J. Solid-State Circuits, 56(12), pp.3560~3572 (2021)
- M. Zhao, "A 4-μW bandwidth", power scalable Delta– Sigma modulator based on swing-enhanced floating inverter amplifiers, 2022, pp.57(3), 709~718
- R. S. A. Kumar, "Analysis and design of a discrete-time delta-sigma modulator using a cascoded floating-inverter-based dynamic amplifier", IEEE J. Solid-State Circuits, 57(11), pp.3384~3395 (2022)
- M. Fukazawa, "A 24-OSR to Simplify Anti- Aliasing Filter 2MHz-BW 83dB-DR 3rd-order DT-DSM using FIA-Based Integrator and Noise-Shaping SAR Combined Digital Noise-Coupling Quantizer", Proc. of 2023 IEEE Symposium on VLSI Technology and Circuits, pp.1~2 (2023)