멀티미디어 전용 명령어를 내장한 멀티코어 프로세서 구현 및 검증
Implementation and Verification of a Multi-Core Processor including Multimedia Specific Instructions
0
조회
0
다운로드
0
인용
0
참고문헌
키워드
초록
In this paper, we present a multi-core processor including multimedia specific instructions to process multimedia data efficiently in the mobile environment. Multimedia specific instructions exploit subword level parallelism (SLP), while the multi-core processor exploits data level parallelism (DLP). These combined parallelisms improve the performance of multimedia processing applications. The proposed multi-core processor including multimedia specific instructions is implemented and tested using a Xilinx ISE 10.1 tool and SoCMaster3 testbed system including Vertex 4 FPGA. Experimental results using a fire detection algorithm show that multimedia specific instructions outperform baseline instructions in the same multi-core architecture in terms of performance (1.2x better), energy efficiency (1.37x better), and area efficiency (1.23x better).
Abstract
In this paper, we present a multi-core processor including multimedia specific instructions to process multimedia data efficiently in the mobile environment. Multimedia specific instructions exploit subword level parallelism (SLP), while the multi-core processor exploits data level parallelism (DLP). These combined parallelisms improve the performance of multimedia processing applications. The proposed multi-core processor including multimedia specific instructions is implemented and tested using a Xilinx ISE 10.1 tool and SoCMaster3 testbed system including Vertex 4 FPGA. Experimental results using a fire detection algorithm show that multimedia specific instructions outperform baseline instructions in the same multi-core architecture in terms of performance (1.2x better), energy efficiency (1.37x better), and area efficiency (1.23x better).
참고문헌 (10)
- E.B. Bourennane, "Cost Comparison of Image Rotation Implementations on Static and Dynamic Reconfigurable FPGAs", Proceedings on the International Conference of Acoustics, Speech, and Signal Processing, 3, pp.3176~3179 (2002)
- X.G. Jiang, "FPGA Implementation of Image Rotation Using Modified Compensated CORDIC", Proceedings on the International Conference of ASIC, 2, pp.752~756 (2005)
- 이시현, "Nios® II 임베디드 프로세서를 사용한 병렬처리 시스템의 설계 및 구현", 한국컴퓨터정보학회논문지, 14(11), pp.97~103 (2009), 한국컴퓨터정보학회
- A. Gentile, "Portable Video Supercomputing", IEEE Trans. on Computers, 53(8), pp.960~973 (2004)
- 박용훈, "매니코어 프로세서 상에서 이산 웨이블릿 변환을 위한 성능 평가 및 분석", 대한임베디드공학회논문지, 7(5), pp.277~284 (2012), 대한임베디드공학회
- 김용민, "JPEG 인코더를 위한 고성능 병렬 프로세서 하드웨어 설계 및 검증", 대한임베디드공학회논문지, 6(2), pp.100~107 (2011), 대한임베디드공학회
- R.B. Lee, "Subword Parallelism with MAX-2", IEEE Micro, 16(4), pp.51~59 (1996)
- S.M. Chai, "Heterogeneous architecture models for interconnect-motivated system design", IEEE Transactions on VLSI Systems, 8(6), pp.660~670 (2000)
- J.C. Eble, "A Generic System Simulator (GENESYS) for ASIC Technology and Architecture beyond 2001", Proceedings on the International Conference of ASIC, pp.193~196 (2001)
- T.X. Truong, "An Effective Four-Stage Smoke-Detection Algorithm using Video Images for Early Fire-Alarm Systems", Fire Safety Journal, 46(5), pp.276~282 (2011)