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첨단 반도체 패키징을 위한 미세 피치 Cu Pillar Bump 연구 동향

Recent Advances in Fine Pitch Cu Pillar Bumps for Advanced Semiconductor Packaging

이효원|윤정원|노은채
한국마이크로전자및패키징학회 (The Microelectronics And Packaging Society)|2023.09|마이크로전자 및 패키징학회지 (Jornal of the Microelectronics and Packaging Society)|제30권 제3호|pp. 1-10|DOI doi.org/10.6117/kmeps.2023.30.3.001

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참고문헌

키워드

Intermetallic compoundDiffusion barrier3D IC PackageMicro-bumpsCu pillar
주제분류재료공학

초록

최근, 고사양 컴퓨터, 모바일 제품의 수요가 증가하면서 반도체 패키지의 고집적화, 고밀도화가 요구된다. 따라서 많은 양의 데이터를 한 번에 전송하기 위해 범프 크기 및 피치 (Pitch)를 줄이고 I/O 밀도를 증가시킬 수 있는 플립 칩(flip-chip), 구리 필러 (Cu pillar)와 같은 마이크로 범프 (Micro-bump)가 사용된다. 하지만 범프의 직경이 70 μm 이하일 경우 솔더 (Solder) 내 금속간화합물 (Intermetallic compound, IMC)이 차지하는 부피 분율의 급격한 증가로 인해 취성이 증가하고, 전기적 특성이 감소하여 접합부 신뢰성을 악화시킨다. 따라서 이러한 점을 개선하기 위해 UBM (Under Bump Metallization) 또는 Cu pillar와 솔더 캡 사이에 diffusion barrier 역할을 하는 층을 삽입시키기도 한다. 본 review 논문에서는 추가적인 층 삽입을 통해 마이크로 범프의 과도한 IMC의 성장을 억제하여 접합부 특성을 향상시키기 위한 다양한 연구를 비교 분석하였다.

Abstract

Recently, as the demand for high-performance computers and mobile products increases, semiconductor packages are becoming high-integration and high-density. Therefore, in order to transmit a large amount of data at once, micro bumps such as flip-chip and Cu pillar that can reduce bump size and pitch and increase I/O density are used. However, when the size of the bumps is smaller than 70 μm, the brittleness increases and electrical properties decrease due to the rapid increase of the IMC volume fraction in the solde r joint, which deteriorates the reliability of the solder joint. Therefore, in order to improve these issues, a layer that serves to prevent diffusion is inserted between the UBM (Under Bump Metallization) or pillar and the solder cap. In this review paper, various studies to improve bonding properties by suppressing excessive IMC growth of micro-bumps through additional layer insertion were compared and analyzed.

참고문헌 (55)

  1. R. James, "The Future of the High-Performance Semiconductor Industry and Design", Proc. 2022 IEEE International Solid-State Circuits Conference(ISSCC), 65, pp.32~35 (2022), IEEE
  2. C. C. Wang, "A new semiconductor package design flow and platform applied on high density fan-out chip", Proc. 2021 71st Electronic Components and Technology Conference (ECTC), pp.112~117 (2021), IEEE
  3. P. Y. Lin, "Reliability Performance of Advanced Organic Interposer (CoWoS®-R) Packages", Proc. 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), pp.723~728 (2021), IEEE
  4. D. Liu, "The influence of molding compound properties on system-in-package reliability for 5G application", Proc. 202122nd International Conference on Electronic Packaging Technology (ICEPT), pp.1~6 (2021), IEEE
  5. T. K. Kim, "Fabrication and Characterization of Three-Dimensional Microelectromechanical System Coaxial Socket Device for Semiconductor Package Testing", Sensors, 23(14), pp.6350~ (2023)
  6. R. Mahajan, "Embedded multidie interconnect bridge—A localized, high-density multichip packaging interconnect", IEEE Trans. Compon. Packaging Manuf. Technol, 9(10), pp.1952~1962 (2019)
  7. A. R. A. Rahman, "Critical challenges and solutions for device miniaturization in integrated circuit pack-aging technology", J. Eng. Appl. Sci, 13(15), pp.6025~6032 (2019)
  8. Z. Chen, "Challenges and prospects for advanced packaging", Fundamental Research (2023)
  9. M. F. Chen, "System on integrated chips (SoIC (TM) for 3D heterogeneous integration", Proc. 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), pp.594~599 (2019), IEEE
  10. Z. Li, "Scaling Solder Micro-Bump Interconnect Down to 10 um Pitch for Advanced 3D IC Packages", Proc. 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), pp.451~456 (2021), IEEE
  11. H. W. Hu, "Development of low temperature CuCu bonding and hybrid bonding for three-dimensional integrated circuits(3D IC)", Microelectron. Reliab, 127, pp.114412~ (2021)
  12. K. N. Tu, "Recent advances on kinetic analysis of solder joint reactions in 3D IC packaging technology", Mater. Sci. Eng. R Rep, 136, pp.1~12 (2019)
  13. K. N. Tu, "Transition from flip chip solder joint to 3D IC microbump : Its effect on microstructure anisotropy", Microelectron. Reliab, 53(1), pp.2~6 (2013)
  14. A. Yu, "Study of 15μm pitch solder microbumps for 3D IC integration", Proc. 2009 59th Electronic Components and Technology Conference (ECTC) (2019), IEEE
  15. S. W. Yoon, "Fabrication and packaging of microbump interconnections for 3D TSV", Proc. 2009 IEEE International Conference on 3D System Integration, pp.1~5 (2009), IEEE
  16. S. Lee, "Development of 3D-IC embedded flexible hybrid system", Proc. 2019 International 3D Systems Integration Conference (3DIC), pp.1~4 (2019), IEEE
  17. A. M. Gusak, "Extremely rapid grain growth in scallop-type Cu6Sn5 during solid–liquid interdiffusion reactions in micro-bump solder joints", Scr. Mater, 179, pp.45~48 (2020)
  18. Y. Miwa, "Characterization of Low-Height Solder Microbump Bonding for Fine-Pitch Inter-Chip Connection in 3DICs", Proc. 2019 International 3D Systems Integration Conference (3DIC), pp.1~4 (2019), IEEE
  19. J. Sylvestre, "Modeling the flip-chip wetting process", IEEE Trans. Compon. Packaging Manuf. Technol, 4(12), pp.2004~2017 (2014)
  20. 김미송, "Flip Chip - Chip Scale Package Bonding Technology with Type 7 Solder Paste Printing", 대한용접접합학회지, 39(4), pp.359~367 (2021), 대한용접접합학회[DOI]
  21. M. Gim, "Highperformance flip chip bonding mechanism study with laser assisted bonding", Proc. 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), pp.1025~1030 (2020), IEEE
  22. S. B. Bulumulla, "A comparison of large I", O flip chip and wire bonded packages, 2001, 1122~1126[DOI]
  23. Y. Yamaji, "A method of fabricating bump-less interconnects applicable to wafer-scale flip-chip bonding", Proc. 2008 10th Electronics Packaging Technology Conference (EPTC), pp.657~662 (2008), IEEE
  24. B. J. Kim, "Intermetallic compound and Kirkendall void growth in Cu pillar bump during annealing and current stressing", Proc. 2008 58th Electronic Components and Technology Conference (ECTC), pp.336~340 (2008), IEEE
  25. G. Gao, "Chip to wafer hybrid bonding with Cu interconnect: High volume manufacturing process compatibility study", Proc. 2019 International Wafer Level Packaging Conference (IWLPC), pp.1~9 (2019), IEEE
  26. N. Islam, "Fine pitch Cu pillar assembly challenges for advanced flip chip package", Proc. 2017 International Wafer Level Packaging Conference (IWLPC), pp.24~25 (2017), IEEE
  27. A. Bao, "Challenges and opportunities of chip package interaction with fine pitch Cu pillar for 28nm", Proc. 2014 IEEE 64th Electronic Components and Technology Conference (ECTC), pp.47~49 (2014), IEEE
  28. P. E. GARROU, "Micro Structure Observation and Reliability Behavior of Peripheral Flip Chip Interconnections with Solder-Capped Cu Pillar Bumps", IEEE Trans. Compon. Packaging Manuf. Technol (2004)
  29. A. Syed, "Cu Pillar and μ-bump electromigration reliability and comparison with high pb, SnPb, and SnAg bumps", Proc. 2011 IEEE 61st Electronic Components and Technology Conference (ECTC), pp.332~339 (2011), IEEE
  30. J. C. Lin, "Investigation of the Growth of Intermetallic Compounds Between Cu Pillars and Solder Caps", J. Electron. Mater, 43, pp.4134~4145 (2014)
  31. H. Y. Hsiao, "Failure mechanism for fine pitch microbump in Cu", Sn, IEEE Trans. Compon. Packaging Manuf. Technol, pp.2015, 5(3)[DOI]
  32. N. Lay, "Pre-applied underfill Technique for Fine-pitch Cu Pillar 3D Die Stacking to Enable 2.5", 3D Advanced Packaging, 2023, pp.2022(1), 273~279
  33. Y. Wang, "Size effect on ductileto-brittle transition in Cu-solder-Cu micro-joints", Proc. 2015IEEE 65th Electronic Components and Technology Conference (ECTC), pp.632~639 (2015), IEEE
  34. L. M. Yin, "Size and volume effects on the strength of microscale lead-free solder joints", J. Electron. Mater, 38(10), pp.2179~2183 (2009)
  35. C. J. Hang, "Growth behavior of Cu", Al intermetallic compounds and cracks in copper ball bonds during isothermal aging, 2008, pp.48(3), 416~424
  36. F. Song, "Investigation of IMC thickness effect on the lead-free solder ball attachment strength: comparison between ball shear test and cold bump pull test results", Proc. 56th Electronic Components and Technology Conference (ECTC), pp.8~ (2006), IEEE
  37. L. Liu, "Effect of solder volume on interfacial reactions between sn3. 5ag0. 75cu solder balls and cu pad", Proc. 2010 11th International Conference on Electronic Packaging Technology & High Density Packaging (ICEPT-HDP), pp.299~304 (2010), IEEE
  38. Y. S. Park, "Effect of fine solder ball diameters on intermetallic growth of Sn-Ag-Cu solder at Cu and Ni pad finish interfaces during thermal aging", Proc. 2011 IEEE 61st Electronic Components and Technology Conference (ECTC), pp.1870~1877 (2011), IEEE
  39. J. W. Yoon, "Jung, "Sequential interfacial intermetallic compound formation of Cu6Sn5 and Ni3Sn4 between Sn–Ag–Cu solder and ENEPIG substrate during a reflow process", J", Alloys Compd, 509(9), pp.L153~L156 (2011)
  40. J. W. Yoon, "Comparative study of ENIG and ENEPIG as surface finishes for a Sn-Ag-Cu solder joint", J. Electron. Mater, 40, pp.1950~1955 (2011)
  41. 유지은, "Intermetallic Compound Growth Induced by Electromigration in Sn-2.5Ag Solder Joints with ENEPIG Surface Finish", 대한용접접합학회지, 40(3), pp.225~232 (2022), 대한용접접합학회[DOI]
  42. N. Chang, "3D micro bump interface enabling top die interconnect to true circuit through silicon via wafer", Proc. 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), pp.1888~1893 (2020), IEEE
  43. C. Y. Ho, "Effects of self-aligned electroplating Cu pillar", SnxAg bump on dense Al lines for chip-to-package connection, 2016, pp.49, 1~7
  44. A. Cassier, "Reliable Testing of Cu Pillar Technology for Smart Devices", Chip Scale Review, 18(5), pp.22~27 (2014)
  45. Y. A. Shen, "Study of grain size and orientation of 30 μm solder microbumps bonded by thermal compression", Proc. 2015 10th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), pp.204~206 (2015), IEEE
  46. Y. J. Chen, "Singlejoint shear strength of micro Cu pillar solder bumps with different amounts of intermetallics", Microelectron. Reliab, 53(1), pp.47~52 (2013)
  47. B. H. Kwak, "Correlations between interfacial reactions and bonding strengths of Cu", Sn, Microelectron. Eng, pp.2012, 89[DOI]
  48. B. J. Kim, "Intermetallic compound growth and reliability of Cu pillar bumps under current stressing", J. Electron. Mater, 39, pp.2281~2285 (2010)
  49. C. Tang, "A Study on the Joint Properties and Reliability of 25μm Cu", Ni, Proc. 2020 21st International Conference on Electronic Packaging Technology (ICEPT), pp.2020[DOI]
  50. M. S. Kim, "Interfacial reactions of fine-pitch Cu", Sn–3. 5 Ag pillar joints on Cu, Ni under bump metallurgies, pp.J. Alloys Compd, 2014[DOI]
  51. Y. B. Park, "Solder Volume Effect on Electromigration Failure Mechanism of Cu", Ni, IEEE Trans. Compon. Packaging Manuf. Technol, pp.2020, 10(10)[DOI]
  52. C. Y. Na, "Fabrication of 30 μm Sn Microbumps by Electroplating and Investigation of IMC Characteristics on Shear Strength", Electronics, 12(1), pp.144~ (2020)
  53. M. Li, "Joule heating induced thermomigration failure in un-powered microbumps due to thermal crosstalk in 2. 5 D IC technology", J. Appl. Phys, 120(7) (2016)
  54. H. K. Cheng, "Microstructural evolution of Cu", solder, Metall. Mater. Trans, pp.2016, 47[DOI]
  55. B. Lee, "Employment of a bi-layer of Ni(P)", Cu as a diffusion barrier in a Cu, Cu bonding structure for three-dimensional interconnects, pp.Acta Mater, 2013[DOI]

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