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Markov Chain Monte Carlo를 이용한 반도체 결함 클러스터링 파라미터의 추정

Estimation of Defect Clustering Parameter Using Markov Chain Monte Carlo

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주제분류산업공학

초록

Negative binomial yield model for semiconductor manufacturing consists of two parameters which are the average number of defects per die and the clustering parameter. Estimating the clustering parameter is quite complex because the parameter has not clear closed form. In this paper, a Bayesian approach using Markov Chain Monte Carlo is proposed to estimate the clustering parameter. To find an appropriate estimation method for the clustering parameter, two typical estimators, the method of moments estimator and the maximum likelihood estimator, and the proposed Bayesian estimator are compared with respect to the mean absolute deviation between the real yield and the estimated yield. Experimental results show that both the proposed Bayesian estimator and the maximum likelihood estimator have excellent performance and the choice of method depends on the purpose of use.

Abstract

Negative binomial yield model for semiconductor manufacturing consists of two parameters which are the average number of defects per die and the clustering parameter. Estimating the clustering parameter is quite complex because the parameter has not clear closed form. In this paper, a Bayesian approach using Markov Chain Monte Carlo is proposed to estimate the clustering parameter. To find an appropriate estimation method for the clustering parameter, two typical estimators, the method of moments estimator and the maximum likelihood estimator, and the proposed Bayesian estimator are compared with respect to the mean absolute deviation between the real yield and the estimated yield. Experimental results show that both the proposed Bayesian estimator and the maximum likelihood estimator have excellent performance and the choice of method depends on the purpose of use.

참고문헌 (17)

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  3. Congdon, P., "Bayesian Models for Categorical Data" (2005), Wiley
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  10. ICE, "Yield and Yield Management, Chapter 3 in Cost Effective IC Manufacturing 1998~1999" (1997), Integrated Circuit Engineering Corporation
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  12. Koren, I., "Defect tolerance in VLSI circuits: Techniques and yield analysis", Proceedings of the IEEE, 86(9), pp.1819~1837 (1998)
  13. Kuo Way, "Reliability, Yield, and Stress Burn-in : An Unified Approach for Microelectronics Systems Manufacturing and Software Development" (1998), Kluwer Academic Publishers
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  16. Stapper, C. H., "Improved yield models for fault-tolerant memory chips", IEEE Transactions on Computers, 42(7), pp.872~881 (1993)
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