본문 바로가기
KERD
논문KCI 등재

공간적 확률 과정 기반의 수율 정보를 이용한 번인과 신뢰성 검사 정책

Differential Burn‐in and Reliability Screening Policy Using Yield Information Based on Spatial Stochastic Processes

1

조회

0

다운로드

0

인용

0

참고문헌

키워드

주제분류산업공학

초록

Decisions on reliability screening rules and burn-in policies are determined based on the estimated reliability. The variability in a semiconductor manufacturing process does not only causes quality problems but it also makes reliability estimation more complicated. This study investigates the nonuniformity characteristics of integrated circuit reliability according to defect density distribution within a wafer and between wafers then develops optimal burn-in policy based on the estimated reliability. New reliability estimation model based on yield information is developed using a spatial stochastic process. Spatial defect density variation is reflected in the reliability estimation, and the defect densities of each die location are considered as input variables of the burn-in optimization. Reliability screening and optimal burn-in policy subject to the burn-in cost minimization is examined,and numerical experiments are conducted.

Abstract

Decisions on reliability screening rules and burn-in policies are determined based on the estimated reliability. The variability in a semiconductor manufacturing process does not only causes quality problems but it also makes reliability estimation more complicated. This study investigates the nonuniformity characteristics of integrated circuit reliability according to defect density distribution within a wafer and between wafers then develops optimal burn-in policy based on the estimated reliability. New reliability estimation model based on yield information is developed using a spatial stochastic process. Spatial defect density variation is reflected in the reliability estimation, and the defect densities of each die location are considered as input variables of the burn-in optimization. Reliability screening and optimal burn-in policy subject to the burn-in cost minimization is examined,and numerical experiments are conducted.

참고문헌 (20)

  1. Barnett, T., "Relating yield models to burnin fall-out in time", IEEE International Test Conference, pp.77~84 (2003)
  2. Barnett, T., "Extending integrated-circuit yield-models to estimate early-life reliability", IEEE Trans. Reliability, 52(3), pp.296~300 (2003)
  3. Bruls, E., "Quality and reliability impact of defect data analysis", IEEE Trans. Semiconductor Manufacturing, 8(2), pp.121~129 (1995)
  4. Cressie, N.A.C., "Statistics for Spatial Data" (1993), John Wiley and Sons
  5. Diggle, P.J., "Statistical Analysis of Spatial Point Patterns" (1983), Academic Press
  6. Gerard, A.A., "Critical area extraction for soft fault estima", IEEE Trans. Semiconductor Manufacturing, 11(1), pp.146~154 (1998)
  7. Gralian, D., "Next generation burn-in development", IEEE Trans. Components, Packaging, and Manufacturing Technology Part B: Advanced Packaging, 17(2), pp.190~196 (1994)
  8. Hwang, J.Y., "Modeling of integrated circuit yield using a spatial nonhomogeneous Poisson process", IEEE Trans. on Semiconductor Manufacturing, 24(3), pp.377~384 (2011)
  9. Huston, H.H., "Reliability defect detection and screening during processing-Theory and implementation", Annual Proceedings of Reliability Physics, pp.268~275 (1992)
  10. "International technology roadmap for semiconductors:2011 edition. Technical report, International Technology Roadmap for Semiconductors" (2011)[URL]
  11. Kiely, P., "Reducing cost with wafer-level test and burnin", Solid State Technology, pp.97~102 (2002)
  12. Kim, T., "Optimal burn-in decision making", Quality and Reliability Engineering International, 14, pp.417~423 (1998)
  13. Kim, T., "A relation model of yield and reliability for the gate oxide failures", Proceedings of Annual Reliability and Maintainability Symposium, pp.428~433 (1998)
  14. Kim, K.O., "A relation model of gate oxide yield and reliability", Microelectronics Reliability, 44, pp.425~434 (2004)
  15. Kuo, W., "Reliability, Yield, and Stress Burn-in" (1998), Kluwer Academic Publishers
  16. Kuper, F., "Relation between yield and reliability of integrated circuits : experimental results and application to continuous early failure rate reduction programs", Proc. Int. Reliability Physics Symp, pp.17~21 (1996)
  17. Lee, J.C., "Modeling and characterization of gate oxide reliability", IEEE Trans. Electronic Devices, 35(12), pp.2268~2278 (1988)
  18. Moeschberger, M.L., "Life tests under competing causes of failure and the theory of competing risks", Biometrics, 27(4), pp.909~933 (1971)
  19. Stapper, C.H., "Modeling of defects in integrated circuit photolithographic patterns", IBM Journal of Research and Development, 28(4), pp.461~475 (1984)
  20. Van der Pol JA, "Relation between yield and reliability of integrated circuits and application to failure rate assessment and reduction in the one digit FIT and PPM reliability era", Microelectronics Reliability, 36(11), pp.1603~1610 (1996)

관련 논문AI추천

이 간행물의 다른 논문 (28건)