Novel test patterns for analog/mixed signal device reliability and electrical parameter extraction
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In this paper, we proposed four test patterns for monitoring of technology and extracting device parameter by using Magnachip/SK hynix 0.18µm analog/mixed signal technology. Firstly, to evaluate interface quality of ultra-thin gate oxide transistor, On-Chip Charge Pumping (OCCP) test pattern was designed. OCCP test pattern consists of Ring Oscillator (RO) and Level shifter module and its maximum frequency is about 500 MHz. But, unfortunately actual OCCP test pattern did not operate except for RO test pattern. Maybe it would be incorrect design of buffer size. So, OCCP design will be modified next Multi-Project Wafer (MPW). Secondly, to estimate photon injection effect, we propose new MOSFET layout structure for high efficient photon injection. Conventional MOSFET has many layers such as ILD, IMD, metal etc. But, our proposed test patterns are designed without these things to analyze optical performance. Thirdly, to evaluate sheet resistance, we proposed kelvin measurement structure. The proposed structure needs less contact pad and area. This test structure expected to reduce at least 40% area compared with conventional kelvin structure. So the exact phonon effects are difficult to estimate. The proposed test pattern has optical path to enhance photon injection efficiency and can help us to measure and analyze optical these effects easily. Fourthly, to estimate the analog performance degradation due to Hot Carrier Injection (HCI), Negative Bias Temperature Instability (NBTI) and Time Dependent Dielectric Breakdown (TDDB), discrete MOSFETs were proposed. Finally, to extract Effective Schottky Barrier Height (ESBH), pn junction diode structures are designed by using CMOS process. With this patterns, we measured ESBH by using activation energy extraction method. In this time, activation energy was measured range from 0.0009 eV to 0.0375 eV.
Abstract
In this paper, we proposed four test patterns for monitoring of technology and extracting device parameter by using Magnachip/SK hynix 0.18µm analog/mixed signal technology. Firstly, to evaluate interface quality of ultra-thin gate oxide transistor, On-Chip Charge Pumping (OCCP) test pattern was designed. OCCP test pattern consists of Ring Oscillator (RO) and Level shifter module and its maximum frequency is about 500 MHz. But, unfortunately actual OCCP test pattern did not operate except for RO test pattern. Maybe it would be incorrect design of buffer size. So, OCCP design will be modified next Multi-Project Wafer (MPW). Secondly, to estimate photon injection effect, we propose new MOSFET layout structure for high efficient photon injection. Conventional MOSFET has many layers such as ILD, IMD, metal etc. But, our proposed test patterns are designed without these things to analyze optical performance. Thirdly, to evaluate sheet resistance, we proposed kelvin measurement structure. The proposed structure needs less contact pad and area. This test structure expected to reduce at least 40% area compared with conventional kelvin structure. So the exact phonon effects are difficult to estimate. The proposed test pattern has optical path to enhance photon injection efficiency and can help us to measure and analyze optical these effects easily. Fourthly, to estimate the analog performance degradation due to Hot Carrier Injection (HCI), Negative Bias Temperature Instability (NBTI) and Time Dependent Dielectric Breakdown (TDDB), discrete MOSFETs were proposed. Finally, to extract Effective Schottky Barrier Height (ESBH), pn junction diode structures are designed by using CMOS process. With this patterns, we measured ESBH by using activation energy extraction method. In this time, activation energy was measured range from 0.0009 eV to 0.0375 eV.