나노미터 MOSFET 파워 게이팅 구조의 노화 현상 분석
Analysis of Aging Phenomena in Nanomneter MOSFET Power Gating Structure
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초록
It has become ever harder to design reliable circuits with each nanometer technology node under normal operation conditions, a tran- sistor device can be affected by various aging effects resulting in performance degradation and eventually design failure. The reliability(aging) effect has traditionally been the area of process engineers. However, in the future, even the smallest of variations can slow downa transistor’s switching speed, and an aging device may not perform adequately at a very low voltage. Because of such dilemmas, thetransistor aging is emerging as a circuit designer’s problem. Therefore, in this paper, the impact of aging effects on the delay and power dissipation of digital circuits by using nanomneter MOSFET power gating structure has been analyzed.. Based on this analyzed aging models, a reliable digital circuits can be designed.
Abstract
It has become ever harder to design reliable circuits with each nanometer technology node under normal operation conditions, a tran- sistor device can be affected by various aging effects resulting in performance degradation and eventually design failure. The reliability(aging) effect has traditionally been the area of process engineers. However, in the future, even the smallest of variations can slow downa transistor’s switching speed, and an aging device may not perform adequately at a very low voltage. Because of such dilemmas, thetransistor aging is emerging as a circuit designer’s problem. Therefore, in this paper, the impact of aging effects on the delay and power dissipation of digital circuits by using nanomneter MOSFET power gating structure has been analyzed.. Based on this analyzed aging models, a reliable digital circuits can be designed.
참고문헌 (9)
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