Word-line and Charge-pump modeling of NAND Flash using Standard CMOS Logic Process
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초록
The industry has increased the word line (WL) layer to improve the density of 3D NAND flash. As the WL layer increases, the energy consumed to generate the boosted WL voltage has also increased. In 3D NAND flash, understanding the block configuration and operation of a word line driver (WL driver) with high energy consumption should be preceded to implement a 3D NAND flash with low energy consumption. This study presents a conventional WL driver for triple-level cell 3D NAND flash to understand the operation and classify energy consumption. The conventional WL driver for a 56-WL layer is fabricated in 180nm UHV process, and it consumes 141.15nJ from a 2.2V during 1 unit of program pulse and verify period.
Abstract
The industry has increased the word line (WL) layer to improve the density of 3D NAND flash. As the WL layer increases, the energy consumed to generate the boosted WL voltage has also increased. In 3D NAND flash, understanding the block configuration and operation of a word line driver (WL driver) with high energy consumption should be preceded to implement a 3D NAND flash with low energy consumption. This study presents a conventional WL driver for triple-level cell 3D NAND flash to understand the operation and classify energy consumption. The conventional WL driver for a 56-WL layer is fabricated in 180nm UHV process, and it consumes 141.15nJ from a 2.2V during 1 unit of program pulse and verify period.
참고문헌 (7)
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- Jong Hak Yuh, "Techniques for the fast settling of word lines in NAND flash memory", US Patent App. 20120075931, SANDISK TECHNOLOGIES, Inc, ~ (2012)
- Raymond Zeng, "A 172mm2 32Gb MLC NAND flash memory in 34nm CMOS", 2009 IEEE International Solid-State Circuits Conference - (ISSCC), pp.236~237 (2009)
- Kim, "Soft Pre-charge H", V Switch for 3D Solid State Drive with NAND Flash Memories, 2013, 339~342