Design Techniques of Energy-Efficient Electrical Neural Recording System
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This paper reviews the design techniques of the electrical neural recording system for energy-efficient operation. To operate neuroprosthetics by decoding action potentials (or neural spikes) and local field potentials in vivo, the electrical neural recording system can be used. For extending the system battery lifetime in vivo and avoiding tissue damage due to the heat, the neural recording system needs to be energy-efficiently driven while consuming low power and achieving low noise performance. In this paper, three energy-efficient design techniques are reviewed with basic properties of the electrical neural recording system: 1) energy-efficient input structure of the operational transconductance amplifier, 2) neural recording front-end channel using the low supply voltage, and 3) neuronal activity-dependent recording system.
Abstract
This paper reviews the design techniques of the electrical neural recording system for energy-efficient operation. To operate neuroprosthetics by decoding action potentials (or neural spikes) and local field potentials in vivo, the electrical neural recording system can be used. For extending the system battery lifetime in vivo and avoiding tissue damage due to the heat, the neural recording system needs to be energy-efficiently driven while consuming low power and achieving low noise performance. In this paper, three energy-efficient design techniques are reviewed with basic properties of the electrical neural recording system: 1) energy-efficient input structure of the operational transconductance amplifier, 2) neural recording front-end channel using the low supply voltage, and 3) neuronal activity-dependent recording system.
참고문헌 (26)
- M. A. Lebedev, "Brainmachine interfaces: past, present and future", Trends in Neurosciences, 29(9), pp.536~546 (2006)
- E. R. Kandel, "Principles of neural science" (2012), McGraw-Hill
- T. Lee, "Multimodal neural interface circuits for diverse interaction with neuronal cell population in human brain", IEEE Trans. Circuits Syst. II, 68(2), pp.574~580 (2021)
- K. D. Wise, "Wireless implantable microsystems:high-density electronic interfaces to the nervous system", Proc. IEEE, 92(1), pp.76~97 (2004)
- "2021 electrode array design catalog"[URL]
- R. R. Harrison, "A low-power lownoise CMOS amplifier for neural recording applications", IEEE J. Solid-State Circuits, 38(6), pp.958~965 (2003)
- R. R. Harrison, "The design of integrated circuits to observe brain activity", Proc. IEEE, 96(7), pp.1203~1216 (2008)
- M. Chae, "Fully-differential selfbiased bio-potential amplifier", Electronics Letters, 44(24), pp.1390~1391 (2008)
- L. Liu, "800 nW 43 nV", √Hz neural recording amplifier with enhanced noise efficiency, 2012, pp.48(9), 479~480
- X. Zou, "A 100-channel 1-mW implantable neural recording IC", IEEE Trans. Circuits Syst. I, 60(10), pp.2584~2596 (2013)
- K. A. Ng, "A low-power, high CMRR neural amplifier system employing CMOS inverterbased OTAs with CMFB through supply rails", IEEE J. Solid-State Circuits, 51(3), pp.724~737 (2016)
- L. Shen, "A 1-V 0.25-μV inverter stacking amplifier with 1.07 noise efficiency factor", IEEE J. Solid-State Circuits, 53(3), pp.896~905 (2018)
- S. Mondal, "A 13.9-nA ECG amplifier achieving 0.86", 0.99 NEF, IEEE J. Solid-State Circuits, pp.2020, 55(2)[DOI]
- R. Muller, "A 0.013mm2, 5 W, DC-coupled neural signal acquisition IC with 0.5 V supply", IEEE J. Solid-State Circuits, 47(1), pp.232~243 (2012)
- D. Han, "A 0.45 V 100-channel neural-recording IC with sub-μ W", channel consumption in 0.18 μ m CMOS, 2013, pp.7(6), 735~746
- F. M. Yaul, "A noise-efficient 36nV", √Hz chopper amplifier using an inverter-based 0.2-V supply input stage, 2017, pp.52(11), 3032~3304
- S.-J. Kim, "A sub-μW", ch analog front-end for Δneural recording with spike-driven data compression, 2019, pp.13(1), 1~14
- R. R. Harrison, "A low-power integrated circuit for a wireless 100-electrode neural recording system", IEEE J. Solid-State Circuits, 42(1), pp.123~133 (2007)
- L. Liu, "Neural recording front-end IC using action potential detection and analog buffer with digital delay for data compression", Proc. Ann. Int. Conf. IEEE Eng. Med. Biol. Soc, pp.745~750 (2013)
- R. H. Olsson III, "A three-dimensional neural recording microsystem with implantable data compression circuitry", IEEE J. Solid-State Circuits, 40(12), pp.2796~2804 (2005)
- B. Gosselin, "A mixed-signal multichip neural recording interface with bandwidth reduction", IEEE Trans. Biomed. Circuits Syst, 3(3), pp.129~141 (2009)
- S. B. Lee, "An inductively powered scalable 32-channel wireless neural recording system-on-a-chip for neuroscience applications", IEEE Trans. Biomed. Circuits Syst, 4(6), pp.360~371 (2010)
- U. Frey, "Switch-matrix-based high-density microelectrode array in CMOS technology", IEEE J. Solid-State Circuits, 45(2), pp.467~482 (2010)
- C. M. Lopez, "An implantable 455-activeelectrode 52-channel CMOS neural probe", IEEE J. Solid-State Circuits, 49(1), pp.248~261 (2014)
- H. Chandrakumar, "A high dynamicrange neural recording chopper amplifier for simultaneous neural recording and stimulation", IEEE J. Solid-State Circuits, 52(3), pp.645~656 (2017)
- H. Chandrakumar, "An 80-mVpp linear-input range, 1.6-GΩ input impedance, lowpower chopper amplifier for closed-loop neural recording that is tolerant to 650-mVpp common-mode interference", IEEE J. Solid-State Circuits, 52(11), pp.2811~2828 (2017)