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A 0.89 μVrms Noise 93 dB High Dynamic Range Low Power 16 Channels Closed-Loop Neural Recording Chip

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초록

The closed-loop neural stimulation system's biggest concern is an artifact with more than tens of mV occurs due to stimulation. Previous studies have digitized the input signals through the analog-to-digital converter (ADC) after using amplifiers to measure tens of μV neural signals. Since the amplifier reduces the input range, the amplifier's output is saturated when a large stimulation artifact appears. This chip design uses the 2nd-order continuous delta-sigma modulator (DSM) to measure signals without saturation even if stimulation artifacts are entered with the neural signal. Overall, circuit structures were designed with a focus on stable operation even if a sudden large signal came in. Also, it can quickly track the sudden change of signals by adding an auto-ranging algorithm. We present 16 channel neural recording chip with a 65-nm CMOS process and the entire chip area is 1 mm2 with 49μW power consumption. Input-referred integrated noise from dc to 500 Hz was 0.89 μVrms, and more than 93 dB input dynamic range were guaranteed.

Abstract

The closed-loop neural stimulation system's biggest concern is an artifact with more than tens of mV occurs due to stimulation. Previous studies have digitized the input signals through the analog-to-digital converter (ADC) after using amplifiers to measure tens of μV neural signals. Since the amplifier reduces the input range, the amplifier's output is saturated when a large stimulation artifact appears. This chip design uses the 2nd-order continuous delta-sigma modulator (DSM) to measure signals without saturation even if stimulation artifacts are entered with the neural signal. Overall, circuit structures were designed with a focus on stable operation even if a sudden large signal came in. Also, it can quickly track the sudden change of signals by adding an auto-ranging algorithm. We present 16 channel neural recording chip with a 65-nm CMOS process and the entire chip area is 1 mm2 with 49μW power consumption. Input-referred integrated noise from dc to 500 Hz was 0.89 μVrms, and more than 93 dB input dynamic range were guaranteed.

참고문헌 (12)

  1. R. R. Harrison, "A low-power low-noise CMOS amplifier for neural recording applications", IEEE Journal of Solid-State Circuits, 38(6), pp.958~965 (2003)
  2. R. R. Harrison, "A Low-Power Integrated Circuit for a Wireless 100-Electrode Neural Recording System", IEEE Journal of Solid-State Circuits, 42(1), pp.123~133 (2007)
  3. D. Han, "A 0.45V 100-channel neural-recording IC with sub-μW", channel consumption in 0.18μm CMOS, 2013 (2013), 290~291
  4. S. Lee, "A 110dB-CMRR 100dB-PSRR multi-channel neural-recording amplifier system using differentially regulated rejection ratio enhancement in 0.18μm CMOS", 2018 IEEE International Solid - State Circuits Conference (ISSCC), pp.472~474 (2018)
  5. F. M. Yaul, "A sub-μW 36nV", √Hz chopper amplifier for sensors using a noise-efficient inverter-based 0.2V-supply input stage, 2016 (2016), 94~95
  6. Jaeouk Cho, "Energy-Efficient Integrated Circuit Solutions Toward Miniaturized Closed-Loop Neural Interface Systems", Frontiers in neuroscience, 15, pp.667447~ (2021)
  7. M. Reza Pazhouhandeh, "Track-and-Zoom Neural Analog-to-Digital Converter with Blind Stimulation Artifact Rejection", IEEE Journal of Solid-State Circuits, 55(7), pp.1984~1997 (2020)
  8. "IEEE Solid-State Circuits Magazine", 10~15
  9. Willy M. Sansen, "Analog Design Essentials", pp.117~147 (2006), Springer
  10. J. -S. Bang, "6.5μW 92.3DB-DR Biopotential-Recording Front-End with 360MVPP Linear Input Range", 2018 IEEE Symposium on VLSI Circuits, pp.239~240 (2018)
  11. H. Chandrakumar, "A 15.2-enob continuous-time ΔΣ adc for a 7.3 μW 200mvpp-linear-input-range neural recording front-end", 2018 IEEE International Solid - State Circuits Conference (ISSCC), pp.232~234 (2018)
  12. C. Kim, "Sub-μVrms-Noise sub-μW", channel ADC-Direct Neural Recording with 200mV, IEEE Journal of Solid-State Circuits, pp.2018, 53(11)[DOI]

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