Hardware Implementation of HEVC CABAC Binary Arithmetic Encoder
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In this paper, hardware architecture of BAE (binary arithmetic encoder) was proposed for HEVC (high efficiency video coding) CABAC (context-based adaptive binary arithmetic coding) encoder. It can encode each bin in a single cycle. It consists of controller, regular encoding engine, bypass encoding engine, and termination engine. The proposed BAE was designed in Verilog HDL, and it was implemented in 180 nm technology. Its operating speed, gate count, and power consumption are 180 MHz, 3,690 gates, and 2.88 mW, respectively.
Abstract
In this paper, hardware architecture of BAE (binary arithmetic encoder) was proposed for HEVC (high efficiency video coding) CABAC (context-based adaptive binary arithmetic coding) encoder. It can encode each bin in a single cycle. It consists of controller, regular encoding engine, bypass encoding engine, and termination engine. The proposed BAE was designed in Verilog HDL, and it was implemented in 180 nm technology. Its operating speed, gate count, and power consumption are 180 MHz, 3,690 gates, and 2.88 mW, respectively.
참고문헌 (8)
- JCTVC-L1003_v34: High efficiency video coding (HEVC) text specification draft 10, "B. Bross", Joint Collaborative Team on Video Coding (JCT-VC), ~ (2013)
- "HEVC software repository HM-11 reference model"[URL]
- 한승목, "저면적 HEVC 코어 변환기 아키텍쳐 설계", 전기전자학회논문지, 17(2), pp.119~128 (2013), 한국전기전자학회[DOI]
- 이종배, "곱셈기를 재사용하는 8×8 HEVC 코어 역변환기 설계", 전기전자학회논문지, 17(4), pp.570~578 (2013), 한국전기전자학회
- Duyen Hai Pham, "Hardware Implementation of HEVC CABAC Binarizer", 전기전자학회논문지, 18(3), pp.356~361 (2014), 한국전기전자학회[DOI]
- M. Wien, "High Efficiency Video Coding" (2014), Springer
- D. Shim, "Understanding of HEVC Standard Technology" (2014), Hongrung Publishing Co.
- Y. Kim, "Design of High Performance Arithmetic Encoder for CABAC in H.264", AVC, 2009, 103~106