확장 가능형 몽고메리 모듈러 곱셈기
A Scalable Montgomery Modular Multiplier
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초록
몽고메리 모듈러 곱셈의 유연한 하드웨어 구현을 위한 확장 가능형 아키텍처를 기술한다. 처리요소 (processing element;PE)의 1차원 배열을 기반으로 하는 확장 가능형 모듈러 곱셈기 구조는 워드 병렬 연산을 수행하며, 사용되는 PE 개수 에따라 연산 성능과 하드웨어 복잡도를 조정하여 구현할 수 있다. 제안된 아키텍처를 기반으로 SEC2에 정의된 8가지 필드 크기를 지원하는 확장 가능형 몽고메리 모듈러 곱셈기(scalable Montgomery modular multiplier; sMM) 코어를 설계했다. 180-nm CMOS 셀 라이브러리로 합성한 결과, sMM 코어는 및 인 경우에 각각 38,317 등가게이트 (GEs) 및139,390 GEs로 구현되었으며, 100 MHz 클록으로 동작할 때, 인 경우에 57만회/초 및 인 경우에 350만회/초의256-비트 모듈러 곱셈을 연산할 수 있는 것으로 평가되었다. sMM 코어는 응용분야에서 요구되는 연산성능과 하드웨어 리소스를 고려하여 사용할 PE 수를 결정함으로써 최적화된 구현이 가능하다는 장점을 가지며, ECC의 확장 가능한 하드웨어 설계에 IP (intellectual property)로 사용될 수 있다.
Abstract
This paper describes a scalable architecture for flexible hardware implementation of Montgomery modular multiplication. Our scalable modular multiplier architecture, which is based on a one-dimensional array of processing elements (PEs),performs word parallel operation and allows us to adjust computational performance and hardware complexity dependingon the number of PEs used, . Based on the proposed architecture, we designed a scalable Montgomery modularmultiplier (sMM) core supporting eight field sizes defined in SEC2. Synthesized with 180-nm CMOS cell library, oursMM core was implemented with 38,317 gate equivalents (GEs) and 139,390 GEs for and , respectively. When operating with a 100 MHz clock, it was evaluated that 256-bit modular multiplications of 0.57 million times/sec for and 3.5 million times/sec for can be computed. Our sMM core has the advantage of enabling anoptimized implementation by determining the number of PEs to be used in consideration of computational performanceand hardware resources required in application fields, and it can be used as an IP (intellectual property) in scalablehardware design of elliptic curve cryptography (ECC).
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