보안 감시용 레이다 시스템을 위한면적-효율적인 특징점 추출기 설계
Design of Area-efficient Feature Extractor for Security Surveillance Radar Systems
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초록
본 논문에서는 보안 감시용 레이다 시스템을 위한 저복잡도 특징점 추출기를 제안하고, 이의 FPGA 기반 설계 결과를 제시하였다. 특징점 추출기의 메모리 요구량을 최소화하기 위해 레이다 스펙트로그램 전체에 대한 통계처리를 요구하는 프레임 단위의 특징점을 배제하고, 단위 도플러 프로파일에서 추출 가능한 특징점을 적용하였다. 제안된 특징점 추출기는Verilog-HDL을 이용하여 RTL 설계 후, Xilinx Zynq-7000 FPGA를 활용하여 구현되었으며, 기존 연구대비 58.3%의 slice 및98.3%의 메모리 요구량을 감소 가능함을 확인하였다. 또한, 제안된 특징점 추출기가 통합된 레이다 기반 보안 감시 시스템을통해 차, 자전거, 보행자 및 전동 킥보드에 대한 분류 실험이 수행되었고, 성능 분석 결과 93.4%의 정확도 성능을 확인하였다.
Abstract
In this paper, an area-efficient feature extractor was proposed for security surveillance radar systems and FPGA-basedimplementation results were presented. In order to reduce the memory requirements, features extracted from Dopplerprofile for FFT window-size are used, while those extracted from total spectrogram for frame-size are excluded. Theproposed feature extractor was design using Verilog-HDL and implemented with Xilinx Zynq-7000 FPGA device. Implementation results show that the proposed design can reduce the logic slice and memory requirements by 58.3% and98.3%, respectively, compared with the existing research. In addition, security surveillance radar system with theproposed feature extractor was implemented and experiments to classify car, bicycle, human and kickboard wereperformed. It is confirmed from these experiments that the accuracy of classification is 93.4%.
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