8가지 블록/키 크기를 지원하는 SPECK 암호 코어
A SPECK Crypto-Core Supporting Eight Block/Key Sizes
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참고문헌
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초록
IoT, 무선 센서 네트워크와 같이 제한된 자원을 갖는 응용분야의 보안에 적합하도록 개발된 경량 블록 암호 알고리듬SPECK의 하드웨어 구현에 관해 기술한다. 블록 암호 SPECK 크립토 코어는 8가지의 블록/키 크기를 지원하며, 회로 경량화를 위해 내부 데이터 패스는 16-비트로 설계되었다. 키 초기화 과정을 통해 복호화에 사용될 최종 라운드 키가 미리생성되어 초기 키와 함께 저장되며, 이를 통해 연속 블록에 대한 암호화/복호화 처리가 가능하도록 하였다. 또한 처리율을 높이기 위해 라운드 연산과 키 스케줄링이 독립적으로 연산되도록 설계하였다. 설계된 SPECK 크립토 코어를 FPGA검증을 통해 하드웨어 동작을 확인하였으며, Virtex-5 FPGA 디바이스에서 1,503 슬라이스로 구현되었고, 최대 동작 주파수는 98 MHz로 추정되었다. 180 nm 공정으로 합성하는 경우, 최대 동작 주파수는 163 MHz로 추정되었으며, 블록/키 크기에 따라 154 Mbps ～ 238 Mbps의 처리량을 갖는다.
Abstract
This paper describes the hardware implementation of SPECK, a lightweight block cipher algorithm developed forthe security of applications with limited resources such as IoT and wireless sensor networks. The block cipherSPECK crypto-core supports 8 block/key sizes, and the internal data-path was designed with 16-bit for small gatecounts. The final round key to be used for decryption is pre-generated through the key initialization process andstored with the initial key, enabling the encryption/decryption for consecutive blocks. It was also designed to processround operations and key scheduling independently to increase throughput. The hardware operation of the SPECKcrypto-core was validated through FPGA verification, and it was implemented with 1,503 slices on the Virtex-5FPGA device, and the maximum operating frequency was estimated to be 98 MHz. When it was synthesized with a180 nm process, the maximum operating frequency was estimated to be 163 MHz, and the estimated throughput wasin the range of 154 ～ 238 Mbps depending on the block/key sizes.
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