Single Device를 사용한 조도센서용 eFuse OTP IP 설계Design of eFuse OTP IP for Illumination Sensors Using Single Devices
Design of eFuse OTP IP for Illumination Sensors Using Single Devices
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초록
조도센서 칩은 아날로그 회로의 트리밍이나 디지털 레지스터의 초기 값을 셋팅하기 위해 소용량의 eFuse(electrical Fuse) OTP(One-Time Programmable) 메모리 IP(Intellectual Property)를 필요로 한다. 본 논문에서는 1.8V LV(Low-Voltage) 로직 소자를 사용하지 않고 3.3V MV(Medium Voltage) 소자만 사용하여 128비트 eFuse OTP IP를 설계하였다. 3.3V 단일 MOS 소자로 설계한 eFuse OTP IP는 1.8V LV 소자의 gate oxide 마스크, NMOS와 PMOS의 LDD implant 마스크에 해당되는 총 3개의마스크에 해당되는 공정비용을 줄일 수 있다. 그리고 1.8V voltage regulator 회로가 필요하지 않으므로 조도센서 칩 사이즈를 줄일 수 있다. 또한 조도센서 칩의 패키지 핀 수를 줄이기 위해 프로그램 전압인 VPGM 전압을 웨이퍼 테스트 동안 VPGM 패드를통해 인가하고 패키징 이후는 PMOS 파워 스위칭 회로를 통해 VDD 전압을 인가하므로 패키지 핀 수를 줄일 수 있다.
Abstract
A light sensor chip requires a small capacity eFuse (electrical fuse) OTP (One-Time Programmable) memory IP(Intellectual Property) to trim analog circuits or set initial values of digital registers. In this paper, 128-bit eFuseOTP IP is designed using only 3.3V MV (Medium Voltage) devices without using 1.8V LV (Low-Voltage) logicdevices. The eFuse OTP IP designed with 3.3V single MOS devices can reduce a total process cost of three maskswhich are the gate oxide mask of a 1.8V LV device and the LDD implant masks of NMOS and PMOS. And sincethe 1.8V voltage regulator circuit is not required, the size of the illuminance sensor chip can be reduced. Inaddition, in order to reduce the number of package pins of the illumination sensor chip, the VPGM voltage, whichis a program voltage, is applied through the VPGM pad during wafer test, and the VDD voltage is applied throughthe PMOS power switching circuit after packaging, so that the number of package pins can be reduced.
참고문헌 (10)
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