낮은 트리거 전압과 높은 홀딩 전압을 가진 SCR 기반의ESD 보호회로에 관한 연구
A Study on SCR-Based ESD Protection Circuits with Low Trigger Voltage and High Holding Voltage
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초록
본 논문에서는 기존 SCR 기반의 ESD 보호회로의 구조적인 변형을 통해 높은 홀딩 전압을 갖는 새로운 ESD 보호회로를 제안한다. 제안된 ESD 보호회로는 LVTSCR(Low Voltage Triggered SCR)과 달리 Anode단을 P-Well에 있는 N+와 연결하여 더 낮은트리거 전압을 유도한 구조이며, 기존 ULVTSCR(Ultra Low Voltage Triggered SCR) 구조에서 N+ Drift와 N-Well을 추가하여홀딩 전압을 개선시킨 구조이다. 제안된 ESD 보호회로는 기생 PNP BJT의 Base 영역인 N+ Drift를 설계 변수로 설정하여 홀딩전압의 개선을 Synopsys 사의 T-CAD Simulation을 통해 검증하였다.
Abstract
This paper proposes a new ESD (Electrostatic Discharge) protection circuit with a high holding voltage bystructurally modifying the traditional SCR (Silicon-Controlled Rectifier)-based ESD protection circuit. The proposedESD protection circuit features a design where, unlike the conventional LVTSCR (Low Voltage Triggered SCR), theanode terminal is connected to the N+ in the P-Well, leading to a lower trigger voltage. Additionally, the structureimproves the holding voltage by incorporating an N+ drift and an N-Well based on the ULVTSCR (Ultra LowVoltage Triggered SCR) design. The proposed ESD protection circuit uses the N+ drift, which serves as the baseregion of the parasitic PNP BJT, as a design variable, and the improvement in holding voltage has been verifiedthrough Synopsys T-CAD simulation.
참고문헌 (5)
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