기약 AOP를 이용한 GF(2m)상의 낮은 지연시간의 시스톨릭 곱셈기
Low Latency Systolic Multiplier over GF(2m)Using Irreducible AOP
0
조회
0
다운로드
3
인용
0
참고문헌
키워드
초록
Efficient finite field arithmetic is essential for fast implementation of error correcting codes and cryptographic applications. Among the arithmetic operations over finite fields, the multiplication is one of the basic arithmetic operations. Therefore an efficient design of a finite field multiplier is required. In this paper, two new bit-parallel systolic multipliers for GF(2m) fields defined by AOP(all-one polynomial) have proposed. The proposed multipliers have a little bit greater space complexity but save at least 22% area complexity and 13% area-time (AT) complexity as compared to the existing multipliers using AOP. As compared to related works, we have shown that our multipliers have lower area-time complexity, cell delay, and latency. So, we expect that our multipliers are well suited to VLSI implementation.
Abstract
Efficient finite field arithmetic is essential for fast implementation of error correcting codes and cryptographic applications. Among the arithmetic operations over finite fields, the multiplication is one of the basic arithmetic operations. Therefore an efficient design of a finite field multiplier is required. In this paper, two new bit-parallel systolic multipliers for GF(2m) fields defined by AOP(all-one polynomial) have proposed. The proposed multipliers have a little bit greater space complexity but save at least 22% area complexity and 13% area-time (AT) complexity as compared to the existing multipliers using AOP. As compared to related works, we have shown that our multipliers have lower area-time complexity, cell delay, and latency. So, we expect that our multipliers are well suited to VLSI implementation.
참고문헌 (14)
- R. E. Blahut, "Theory and Practice of Error Control Codes" (1983), Addison-Wesley
- R. Lidl, "Introduction to Finite Fields and Their Applications" (1994), Cambridge University Press
- 김기원, "유한체 GF(2m)상의 낮은 지연시간의 AB2 곱셈 구조 설계", 대한임베디드공학회논문지, 7(2), pp.79~84 (2012), 대한임베디드공학회[DOI]
- 정찬복, "단일 데이터패스 구조에 기반한 AES 암호화 및 복호화 엔진의 효율적인 통합설계", 대한임베디드공학회논문지, 7(3), pp.121~127 (2012), 대한임베디드공학회[DOI]
- C.L. Wang, "Systolic Array Implementation of Multipliers for finite fields GF(2m)", IEEE Transactions on Circuits and Systems II, 38(7), pp.796~800 (1991)
- C.Y. Lee, "Bit-Parallel Systolic Multipliers for GF(2m) Fields Defined by All-One and Equally-Spaced Polynomials", IEEE Transactions on Computers, 50(5), pp.385~393 (2001)
- C.Y. Lee, "Low-Complexity Bit-Parallel Systolic Architecture for Computing AB2+C in a Class of Finite Field GF(2m)", IEEE Transactions on Circuits and Systems II, 48(5), pp.519~523 (2001)
- 권순학, "기약 All One Polynomial을 이용한 유한체 GF(m)상의 시스톨릭 곱셈기 설계+", 한국통신학회논문지C, 29(8), pp.1047~1054 (2004), 한국통신학회
- 김태완, "기약 AOP를 이용한 GF(2m)상의 낮은 복잡도와 지연시간을 가지는 비트-병렬 시스톨릭 곱셈 구조", 한국정보기술학회논문지, 11(3), pp.133~139 (2013), 한국정보기술학회
- K.W. Kim, "Design of a Low-Latency Multiplication Algorithm for Finite Fields", pp.271~278 (2016)
- T. Itoh, "Structure of Parallel Multipliers for a Class of Fields GF(2m)", Information and Computation, 83(1), pp.21~40 (1989)
- M.A. Hasan, "Modular Construction of Low Complexity Parallel Multipliers for a Class of Finite Fields GF(2m)", IEEE Transactions on Computers, 41(8), pp.962~971 (1992)
- N. Weste, "Principles of CMOS VLSI design" (1993), Addison-Wesley
- S. M. Kang, "CMOS Digital Integrated Circuits Analysis and Design" (1999), McGraw-Hill