유한체 GF(2m)상의 낮은 지연시간의 AB2 곱셈 구조 설계
Design of Low-Latency Architecture for AB2 Multiplication over Finite Fields GF(2m)
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초록
Efficient arithmetic design is essential to implement error correcting codes and cryptographic applications over finite fields. This article presents an efficient AB2 multiplier in GF(2m) using a polynomial representation. The proposed multiplier produces the result in m clock cycles with a propagation delay of two AND gates and two XOR gates using O(m2) area-time complexity. The proposed multiplier is highly modular, and consists of regular blocks of AND and XOR logic gates. Especially, exponentiation, inversion, and division are more efficiently implemented by applying AB2 multiplication repeatedly rather than AB multiplication. As compared to related works, the proposed multiplier has lower area-time complexity, computational delay, and execution time and is well suited to VLSI implementation.
Abstract
Efficient arithmetic design is essential to implement error correcting codes and cryptographic applications over finite fields. This article presents an efficient AB2 multiplier in GF(2m) using a polynomial representation. The proposed multiplier produces the result in m clock cycles with a propagation delay of two AND gates and two XOR gates using O(m2) area-time complexity. The proposed multiplier is highly modular, and consists of regular blocks of AND and XOR logic gates. Especially, exponentiation, inversion, and division are more efficiently implemented by applying AB2 multiplication repeatedly rather than AB multiplication. As compared to related works, the proposed multiplier has lower area-time complexity, computational delay, and execution time and is well suited to VLSI implementation.
참고문헌 (13)
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