High-Performance Parallelization Methodology for Heterogeneous HPC Platforms
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초록
Latest High Performance Computing (HPC) platforms are built with heterogeneous chips such as multicore microprocessors and multicore GPUs (Graphic Processing units), thus they are commonly called as Heterogeneous HPC platforms. Parallelizing applications on such platforms is mostly dominated by SIMD style of parallelism mainly to exploit GPUs’ excellent floating-point performance. However, it is a restricted parallel execution model because the multiple CPU cores are not usually participating in the parallel execution, thus the full performance potential of heterogeneous architectures is not exploited. In this paper, we propose a generalized parallelization methodology to efficiently map applications onto the heterogeneous HPC architectures in order to fully exploit their performance potential. For the methodology, we develop strategies to map parallel tasks onto different components of the heterogeneous architectures based on their application characteristics and the computing demands. A general parallel execution model beyond SIMD is adopted in the task mapping.
Abstract
Latest High Performance Computing (HPC) platforms are built with heterogeneous chips such as multicore microprocessors and multicore GPUs (Graphic Processing units), thus they are commonly called as Heterogeneous HPC platforms. Parallelizing applications on such platforms is mostly dominated by SIMD style of parallelism mainly to exploit GPUs’ excellent floating-point performance. However, it is a restricted parallel execution model because the multiple CPU cores are not usually participating in the parallel execution, thus the full performance potential of heterogeneous architectures is not exploited. In this paper, we propose a generalized parallelization methodology to efficiently map applications onto the heterogeneous HPC architectures in order to fully exploit their performance potential. For the methodology, we develop strategies to map parallel tasks onto different components of the heterogeneous architectures based on their application characteristics and the computing demands. A general parallel execution model beyond SIMD is adopted in the task mapping.
참고문헌 (20)
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